APPLICATIONS INFOR
參數(shù)資料
型號: LTC1590CN#PBF
廠商: Linear Technology
文件頁數(shù): 12/12頁
文件大小: 0K
描述: IC D/A CONV 12BIT DUAL 16-DIP
產(chǎn)品培訓模塊: LTC275x 18-Bit DAC
標準包裝: 25
設置時間: 1.5µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 55µW
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應商設備封裝: 16-PDIP
包裝: 管件
輸出數(shù)目和類型: 4 電流,單極;4 電流,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 1349 (CN2011-ZH PDF)
9
LTC1590
APPLICATIONS INFORMATION
WU
U
Op Amp Selection
To maintain the excellent accuracy and stability of the
LTC1590 thought should be given to op amp selection.
Fortunately, the sensitivity of INL and DNL to op amp offset
has been significantly reduced compared to competing
parts of this type. The op amp’s VOS causes DAC output
offset. In addition, because the DAC’s equivalent output
resistance RO changes as a function of code, there is a
code-dependent DAC output error proportional to VOS. For
fixed reference applications this causes gain, INL and DNL
error. For multiplying applications, a code-dependent, DC
output voltage error is seen. At zero scale the DAC output
error is equal to the op amp offset, and at full scale the
output error is equal to twice the op amp offset. For
example, a 1mV op amp offset will cause a 0.41LSB zero-
scale error and a 0.82LSB full-scale error with a 10V full-
scale range. The offset caused INL error is approximately
0.4 times the op amp VOS and DNL error is 0.07 times op
amp VOS. For the same example of 1mV op amp VOS and
10V full-scale range, the INL degradation will be 0.17LSB
and DNL degradation will be 0.03LSB.
Op amp bias current causes only an offset error equal to
(IBIAS)(RFB) ≈ (IBIAS)(11k). For example, a 100nA op
amp bias current causes a 1.1mV DAC offset, or 0.45LSB
for a 10V full-scale range. It is important to note that
connecting the op amp noninverting input to ground
through a resistor will not cancel bias current errors and
should never be done! Similarly an offset caused by op
amp bias current should not be adjusted by using the op
amp null pins since this increases offset between DAC
OUT1 and OUT2 pins, causing INL, DNL and gain errors.
If op amp offset error adjustment is required, the op amp
input offset voltage (the voltage difference between OUT1
and OUT2) should be nulled.
Grounding
As with any high precision data converter, clean ground-
ing is important. A low impedance analog ground plane
and star grounding should be used. OUT2 carries the
complementary DAC output current and should be tied to
the star ground with as low a resistance as possible. Other
ground points that must be tied to the star ground point
include the VREF input ground, the op amp noninverting
input(s) and the VOUT ground reference point.
13
14
11
12
15
DATA IN
SERIAL CLOCK
CHIP SELECT/DAC LOAD
DATA OUT
CLEAR
16
98
1
2
10
1590 TA07
3
5
7
1
8
6
4
5
6
2
3
4
VOUT B
VOUT A
5V
VIN B
±10V
VIN A
±10V
7
33pF
0.1
F
0.01
F
33pF
15V
–15V
0.01
F
VOUT = –VIN
D
4096
()
DAC B
VREF B
RFB B
VREF A
RFB A
DAC A
24-BIT
SHIFT
REG
AND
LATCH
DIN
CLK
CS/LD
DOUT
CLR
DGND
AGND
LTC1590
OUT1 B
OUT2 B
OUT2 A
OUT1 A
+
+
1/2
LT1358
1/2
LT1358
TYPICAL APPLICATIONS
U
Dual Programmable Attenuator
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