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參數資料
| 型號： | LTC1598CG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 25kSPS ADC Serial-Out, On-Chip 11-Ch. Analog MUX 20-PDIP |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-24 |
| 文件頁數： | 14/24頁 |
| 文件大?。?/td> | 430K |
| 代理商： | LTC1598CG |
14
LTC1594/LTC1598
APPLICATIO
S I
FOR
ATIO
U
W
U
U
CLK
EN
D1
D2
CSMUX
CSADC
B5
B6
B7
B8
B9
B10
B11
D
OUT
CH0 TO
CH7
D
IN
t
CONV
t
suCS
NULL
BIT
D0
B4
B3
B2
B1
B0
EN
D1
t
SMPL
t
ON
t
ON
B5
B6
B7
B8
B9
B10
B11
t
CONV
t
suCS
NULL
BIT
D0
D2
EN
D1
D0
D2
B4
B3
B2
B1
B0
t
SMPL
ADCIN =
MUXOUT
COM = GND
1594/98 F05
B4
B3
B2
B1
B0
DON’T CARE
DON’T CARE
MUXOUT/ADCIN Loop Economizes
Signal Conditioning
The MUXOUT and ADCIN pins of the LTC1594/LTC1598
form a very flexible external loop that allows Program-
mable Gain Amplifier (PGA) and/or processing analog
input signals prior to conversion. This loop is also a cost
effective way to perform the conditioning, because only
one circuit is needed instead of one for each channel.
In the Typical Applications section, there are a few
examples illustrating how to use the MUXOUT/ADCIN loop
to form a PGA and to antialias filter several analog inputs.
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 320
μ
A and automatic
shutdown between conversions, the LTC1594/LTC1598
achieve extremely low power consumption over a wide
range of sample rates (see Figure 6). The auto shutdown
allows the supply current to drop with reduced sample
rate. Several things must be taken into account to achieve
such a low power consumption.
Shutdown
The LTC1594/LTC1598 are equipped with automatic shut-
down features. They draw power when the CS pin is low.
The bias circuits and comparator of the ADC powers down
and the reference input becomes high impedance at the
end of each conversion leaving the CLK running to clock
out the LSB first data or zeroes (see Figures 1 and 2). When
the CS pin is high, the ADC powers down completely
leaving the CLK running to clock the input data word into
MUX. If the CS, D
IN
and CLK are not running rail-to-rail, the
input logic buffers will draw currents. These currents may
be large compared to the typical supply current. To obtain
the lowest supply current, run the CS, D
IN
and CLK pins
rail-to-rail.
D
OUT
Loading
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the D
OUT
pin
can add more than 80mA to the supply current at a
320kHz clock frequency. An extra 80mA or so of current
goes into charging and discharging the load capacitor.
The same goes for digital lines driven at a high frequency
by any logic. The (C)(V)(f) currents must be evaluated
and the troublesome ones minimized.
Figure 5. Use Separate Chip Selects to Maximize Sample Rate
SAMPLE FREQUENCY (kHz)
0.1
1
S
μ
A
10
100
1000
1
10
100
1594/98 F06
T
A
= 25
°
C
V
CC
= 5V
V
REF
= 5V
f
CLK
= 320kHz
Figure 6. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
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