參數(shù)資料
型號(hào)： LTC1598CG
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 8-Bit, 25kSPS ADC Serial-Out, On-Chip 11-Ch. Analog MUX 20-PDIP
中文描述： 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封裝： 0.209 INCH, PLASTIC, SSOP-24
文件頁(yè)數(shù)： 16/24頁(yè)
文件大?。?/td> 430K
代理商： LTC1598CG
16
LTC1594/LTC1598
APPLICATIO
S I
FOR
ATIO
U
edge, the S & H goes into hold mode and the conversion
begins. The voltage on the “COM” input must remain
constant and be free of noise and ripple throughout the
conversion time. Otherwise, the conversion operation
may not be performed accurately. The conversion time is
12 CLK cycles. Therefore, a change in the “COM” input
voltage during this interval can cause conversion errors.
For a sinusoidal voltage on the “COM” input this error
would be:
V
ERROR(MAX)
= V
PEAK
(2
π
)(f)(“COM”)12/f
CLK
Where f(“COM”) is the frequency of the “COM” input
voltage, V
PEAK
is its peak amplitude and f
CLK
is the
frequency of the CLK. In most cases V
ERROR
will not be
significant. For a 60Hz signal on the “COM” input to
generate a 1/4LSB error (305
μ
V) with the converter
running at CLK = 320kHz, its peak value would have to be
8.425mV.
W
U
U
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1594/
LTC1598 have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used
or if slow settling op amps drive the inputs, care must be
taken to insure that the transients caused by the current
spikes settle completely before the conversion begins.
“Analog” Input Settling
The input capacitor of the LTC1594/LTC1598 is switched
onto the selected channel input during the t
SMPL
time (see
Figure 7) and samples the input signal within that time. The
sample phase is at least 1 1/2 CLK cycles before conver-
sion starts. The voltage on the “analog” input must settle
completely within t
SMPL
. Minimizing R
SOURCE+
and C1 will
improve the input settling time. If a large “analog” input
source resistance must be used, the sample time can be
increased by using a slower CLK frequency.
“COM” Input Settling
At the end of the t
SMPL
, the input capacitor switches to the
“COM” input and conversion starts (see Figures 1 and 7).
During the conversion, the “analog” input voltage is
effectively “held” by the sample-and-hold and will not
affect the conversion result. However, it is critical that the
“COM” input voltage settles completely during the first
CLK cycle of the conversion time and be free of noise.
Minimizing R
SOURCE–
and C2 will improve settling time.
If a large “COM” input source resistance must be used,
the time allowed for settling can be extended by using a
slower CLK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the “analog” and “COM” input
sampling times can be extended as described above to
accommodate slower op amps. Most op amps, including
the LT
1006 and LT1413 single supply op amps, can be
made to settle well even with the minimum settling
windows of 4.8
μ
s (“analog” input) which occur at the
maximum clock rate of 320kHz.
Source Resistance
The analog inputs of the LTC1594/LTC1598 look like a
20pF capacitor (C
IN
) in series with a 500
resistor (R
ON
)
and a 45
channel resistance as shown in Figure 8.
C
IN
gets switched between the selected “analog” and
“COM” inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC
time constants be short enough to allow the analog
inputs to completely settle within the allowed time.
Figure 8. Analog Input Equivalent Circuit
R
ON
500
R
ON
45
C
20pF
LTC1594
LTC1598
“ANALOG”
INPUT
R
SOURCE
+
V
IN
+
C1
“COM”
INPUT
MUXOUT
MUX
ADCIN
R
SOURCE
–
V
IN
–
C2
1594/98 F08
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