VREF R1 7.5k 3 4" />
參數(shù)資料
型號: LTC1608ACG#TR
廠商: Linear Technology
文件頁數(shù): 5/20頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 5V SAMPLING 36SSOP
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 16
采樣率(每秒): 500k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 420mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 36-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 36-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
13
LTC1608
APPLICATIO S I FOR ATIO
WU
UU
R2
12k
R3
16k
REFERENCE
AMP
22
F
REFCOMP
AGND
VREF
R1
7.5k
3
4
5
2.500V
4.375V
LTC1608
1608 F12a
BANDGAP
REFERENCE
Figure 12a. LTC1608 Reference Circuit
1
2
3
0.1
F
22
F
ANALOG
INPUT
1608 F12b
LT1019A-2.5
VOUT
VIN
5V
AIN
+
AIN
VREF
LTC1608
AGND
REFCOMP
5
4
+
Figure 12b. Using the LT1019-2.5 as an External Reference
A 7.5k resistor is in series with the output so that it can be
easily overdriven by an external reference or other
circuitry (see Figure 12b). The reference amplifier gains
the voltage at the VREF pin by 1.75 to create the required
internal reference voltage. This provides buffering
between the VREF pin and the high speed capacitive DAC.
The reference amplifier compensation pin (REFCOMP, Pin
4) must be bypassed with a capacitor to ground. The
reference amplifier is stable with capacitors of 22
F or
greater. Using a 0.1
Fceramicinparallelisrecommended.
The VREF pin can be driven with a DAC or other means
shown in Figure 13. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1608 reference amplifier will limit
the bandwidth and settling time of this circuit. A settling
time of 20ms should be allowed for after a reference
adjustment.
LTC1608
AIN
+
ANALOG INPUT
2V TO 2.7V
DIFFERENTIAL
AIN
VREF
REFCOMP
AGND
1608 F13
1
2
3
4
5
22
F
LTC1450
2V TO 2.7V
Figure 13. Driving VREF with a DAC
Figure 14a. CMRR vs Input Frequency
INPUT FREQUENCY (Hz)
1k
COMMON
MODE
REJECTION
(dB)
80
70
60
50
40
30
20
10
0
10k
100k
1608 G14a
1M
Differential Inputs
The LTC1608 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of AIN+ – AIN– independent of the
common mode voltage (see Figure 15a). The common
mode rejection holds up to extremely high frequencies
(see Figure 14a). The only requirement is that both inputs
can not exceed the AVDD or VSS power supply voltages.
Integral nonlinearity errors (INL) and differential nonlin-
earity errors (DNL) are independent of the common mode
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
common mode voltage. Dynamic performance is also
affected by the common mode voltage. THD will degrade
as the inputs approach either power supply rail, from 96dB
with a common mode of 0V to 86dB with a common mode
of 2.5V or – 2.5V.
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