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參數(shù)資料
| 型號： | LTC1608ACG#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 5V SAMPLING 36SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 420mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
15
LTC1608
APPLICATIO S I FOR ATIO
WU
UU
applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1608 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN– leads
will be rejected by the input CMRR. The AIN– input can be
used as a ground sense for the AIN+ input; the LTC1608
will hold and convert the difference voltage between AIN+
and AIN–. The leads to AIN+ (Pin 1) and AIN– (Pin 2) should
be kept as short as possible. In applications where this is
not possible, the AIN+ and AIN– traces should be run side
by side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10
F or 22F
bypass capacitors should be used at the VDD andREFCOMP
pins as shown in Figure 16 and in the Typical Application
on the first page of this data sheet. Surface mount ceramic
capacitors such as Taiyo Yuden’s LMK325BJ106MN and
LMK432BJ226MM provide excellent bypassing in a small
board space. Alternatively, 10
F tantalum capacitors in
parallel with 0.1
F ceramic capacitors can be used. By-
pass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
EXAMPLE LAYOUT
Figures 17a, 17b, 17c, 17d and 17e show the schematic
and layout of an evaluation board. The layout demon-
strates the proper use of decoupling capacitors and ground
plane with a 4-layer printed circuit board.
DC PERFORMANCE
The noise of an ADC can be evaluated in two ways: signal-
to-noise raio (SNR) in frequency domain and histogram in
time domain. The LTC1608 excels in both. Figure 19a
demonstrates that the LTC1608 has an SNR of over 90dB
in frequency domain. The noise in the time domain histo-
gram is the transition noise associated with a high resolu-
tion ADC which can be measured with a fixed DC signal
applied to the input of the ADC. The resulting output codes
are collected over a large number of conversions. The
shape of the distribution of codes will give an indication of
the magnitude of the transition noise. In Figure 18, the
distribution of output codes is shown for a DC input that
has been digitized 4096 times. The distribution is Gaussian
and the RMS code transition noise is about 0.66LSB. This
corresponds to a noise level of 90.9dB relative to full scale.
Adding to that the theoretical 98dB of quantization error
for 16-bit ADC, the resultant corresponds to an SNR level
of 90.1dB which correlates very well to the frequency
domain measurements in Dynamic Performance section.
DYNAMIC PERFORMANCE
The LTC1608 has excellent high speed sampling capabil-
ity. Fast fourier transform (FFT) test techniques are used
to test the ADC’s frequency response, distortions and
Figure 16. Power Supply Grounding Practice
1608 F16
AIN
+
VSS
OVDD
DGND
AVDD
LTC1608
DIGITAL
SYSTEM
ANALOG
INPUT
CIRCUITRY
AGND
5, 6, 7, 8
2
34
29
DVDD
OGND
28
10
1
REFCOMP
4
22
F
VREF
3
2.2
F
AIN
–
10
F
36
10
F
AVDD
35
10
F
10
F
+
–
9
10
F
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