參數(shù)資料
型號(hào): LTC1700
廠商: Linear Technology Corporation
英文描述: Quadruple 2-Input Exclusive-OR Gates 14-SO 0 to 70
中文描述: 無檢測(cè)電阻同步升壓型DC / DC控制器
文件頁數(shù): 5/16頁
文件大?。?/td> 194K
代理商: LTC1700
LTC1700
5
SGND (Pin 1):
Small-Signal Ground. Must be routed
separately from other grounds to the (–) terminal of C
OUT
.
I
TH
(Pin 2):
Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.18V.
V
FB
(Pin 3):
Receives the feedback voltage from an exter-
nal resistive divider across the output capacitor.
RUN/SS (Pin 4):
Combination of Soft-Start and Run
Control Inputs. A capacitor to ground at this pin sets the
ramp time to full output current. The time is approximately
0.45s/
μ
F. Forcing this pin below 1.08V causes all circuitry
to be shut down.
SYNC/MODE (Pin 5):
This pin performs three functions. A
voltage greater than 1.2V on this pin allows Burst Mode
operation at low load currents, while grounding or apply-
ing a clock signal on this pin defeats Burst Mode operation.
An external clock between 400kHz and 750kHz applied to
this pin forces the LTC1700 to operate at the external clock
frequency. Do not attempt to synchronize below 400kHz
or above 750kHz.
TG (Pin 6):
Top Gate Drive. Drives the external synchro-
nous P-channel MOSFET with a voltage swing between 0V
to V
OUT
.
V
OUT
(Pin 7):
This pin performs two functions. It serves as
the supply pin and also as one of the inputs to the current
reversal comparator.
BG (Pin 8):
Bottom Gate Drive. Drives the external main
N-channel MOSFET with a voltage swing between 0V to
V
OUT
.
PGND (Pin 9):
Top and Bottom Gate Drivers Ground.
Connects to the (–) terminal of C
OUT
. Source of the main
N-channel MOSFET must be connected close to this pin
since this pin is also one of the inputs to the V
DS
sense
amplifier.
SW (Pin 10):
This pin connects to the inputs of two
comparators: The V
DS
sense amplifier and the current
reversal comparator. The drain of an internal N-channel
start-up MOSFET (M1) is also connected to this pin.
PI
FU
CTIO
N
S
U
U
Load Step Transient Response
Burst Mode Operation Inhibited
Load Step Transient Response
Burst Mode Operation Enabled
Load Step Transient Response
Burst Mode Operation Inhibited
TYPICAL PERFOR
M
A
CE CHARACTERISTICS
U
V
IN
= 3.3V
V
OUT
= 5V
2A/DIV
V
IN
= 4.2V
V
OUT
= 5V
2A/DIV
V
SYNC
= V
IN
LOAD STEP = 100mA TO 1.7A
V
IN
= 4.2V
V
OUT
= 5V
2A/DIV
V
SYNC
= 0V
LOAD STEP = 100mA TO 1.7A
V
SYNC
= 0V
LOAD STEP = 100mA TO 1.7A
A/C COUPLED
OUTPUT
VOLTAGE
(0.2V/DIV)
INDUCTOR
CURRENT
(2A/DIV)
A/C COUPLED
OUTPUT
VOLTAGE
(0.2V/DIV)
INDUCTOR
CURRENT
(2A/DIV)
A/C COUPLED
OUTPUT
VOLTAGE
(0.2V/DIV)
INDUCTOR
CURRENT
(2A/DIV)
1700 G13
1700 G15
1700 G14
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