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參數(shù)資料
| 型號(hào)： | LTC1708-PG |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Dual Adjustable 5-Bit VID High Efficiency, 2-Phase Current Mode Synchronous Buck Regulator Controller |
| 中文描述： | 可調(diào)式雙5位VID高效率，2相電流模式同步降壓穩(wěn)壓控制器 |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 358K |
| 代理商： | LTC1708-PG |
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LTC1708-PG
required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV
CC
current results in approxi-
mately 2.5mA of V
IN
current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from V
IN
) to only a few percent.
3. I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
SENSE
,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R
DS(ON)
, then the resistance of one
MOSFET can simply be summed with the resistances of
L, R
SENSE
and ESR to obtain I
2
R losses. For example, if
each R
DS(ON)
= 10m
, R
L
= 5m
, R
SENSE
= 3m
and
R
ESR
= 10m
(sum of both input and output capacitance
losses), then the total resistance is 28m
. This results in
losses ranging from 3% to 8% as the output current
increases from 5A to 15A for a 5V output, or an 8% to 20%
loss for a 1.6V output. Efficiency varies as the inverse
square of V
OUT
for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) V
IN2
I
O(MAX)
C
RSS
f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C
IN
has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20
μ
F to 40
μ
F of capacitance having a
maximum of 20m
to 50m
of ESR. The LTC1708 2-
phase architecture typically halves this input capacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead-time
and inductor core losses generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to
I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
.
I
LOAD
also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the I
TH
pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
TH
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
The I
TH
series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 100%
of full-load current having a rise time of 1
μ
s to 10
μ
s will
produce output voltage and I
TH
pin waveforms that will
APPLICATIU
W
U
U
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