VIH High Level Input Voltage
參數(shù)資料
型號: LTC1740IG#TR
廠商: Linear Technology
文件頁數(shù): 11/16頁
文件大?。?/td> 0K
描述: IC ADC SMPL 14BIT 6MSPS 36-SSOP
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
采樣率(每秒): 6M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 300mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 36-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
4
LTC1740
1740f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
VDD = 5.25V, VSS = 0V
q
2.4
V
VDD = 5.25V, VSS = – 5V
q
2.4
V
VIL
Low Level Input Voltage
VDD = 4.75V, VSS = 0V
q
0.8
V
VDD = 4.75V, VSS = – 5V
q
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
q
±10
A
CIN
Digital Input Capacitance
1.8
pF
VOH
High Level Output Voltage
0VDD = 4.75V, IO = –10A
4.74
V
0VDD = 4.75V, IO = –200A
q
4.0
4.71
V
0VDD = 2.7V, IO = –10A
2.6
V
0VDD = 2.7V, IO = –200A
q
2.3
V
VOL
Low Level Output Voltage
0VDD = 4.75V, IO = 160A
0.05
V
0VDD = 4.75V, IO = 1.6mA
q
0.10
0.4
V
0VDD = 2.7V, IO = 160A
0.05
V
0VDD = 2.7V, IO = 1.6mA
q
0.10
0.4
V
ISOURCE
Output Source Current
VOUT = 0V, 0VDD = 5V
50
mA
ISINK
Output Sink Current
VOUT = VDD, 0VDD = 5V
35
mA
The q denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single
supply operation. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Positive Supply Voltage
(Note 9)
4.75
5.25
V
OVDD
Output Supply Voltage
(Note 9)
2.7
VDD
V
VSS
Negative Supply Voltage
Dual Supply Mode
– 5.25
– 4.75
V
Single Supply Mode
0
V
IDD
Positive Supply Current
q
47
60
mA
ISS
Negative Supply Current
q
2.3
2.6
mA
PD
Power Dissipation
q
245
300
mW
The q denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE
Sampling Frequency
q
0.05
6
MHz
tCONV
Conversion Time
q
100
135
ns
tACQ
Acquisition Time
(Note 9)
q
31
67
ns
tH
CLK High Time
(Note 9)
q
20
83.3
ns
tL
CLK Low Time
(Note 9)
q
20
83.3
ns
tAP
Aperature Delay of Sample-and-Hold
– 900
ps
t1
CLK
↑ to BUSY↓
3.5
ns
t2
BUSY
↑ to Outputs Valid
1.5
ns
Data Latency
3
Cycles
The q denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 4)
DIGITAL I PUTS A D DIGITAL OUTPUTS
U
POWER REQUIRE E TS
W
U
TI I G CHARACTERISTICS
U
W
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