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參數(shù)資料
| 型號： | LTC1740IG#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 0K |
| 描述： | IC ADC SMPL 14BIT 6MSPS 36-SSOP |
| 標準包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 6M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 300mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
13
LTC1740
1740f
Full-Scale and Offset Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error should be adjusted before full-scale error. Figure 11
shows a method for error adjustment for a dual supply,
5.00V input range application. For zero offset error apply
– 0.15mV (i. e., – 0.5LSB) at + AIN and adjust R1 until the
output code flickers between 00 0000 0000 0000 and 11
1111 1111 1111. For full-scale adjustment, apply an input
voltage of 2.49954V (FS – 1.5LSBs) at + AIN and adjust R2
until the output code flickers between 01 1111 1111 1110
and 01 1111 1111 1111.
Digital Output Drivers
The LTC1740 output drivers can interface to logic operat-
ing from 3V to 5V by setting OVDD to the logic power
supply. OVDD requires a 1F decoupling capacitor. To
prevent digital noise from affecting performance, the load
capacitance on the digital outputs should be minimized. If
large capacitive loads are required, (>30pF) external buff-
ers or 100
resistors in series with the digital outputs are
suggested.
Timing
The conversion start is controlled by the rising edge of the
CLK pin. Once a conversion is started it cannot be stopped
or restarted until the conversion cycle is complete. Output
data is updated at the end of conversion, or about 100ns
after a conversion is begun. There is an additional two
cycle pipeline delay, so the data for a given conversion is
output two full clock cycles plus 100ns after the convert
start. Thus output data can be latched on the third CLK
rising edge after the rising edge that samples the input.
Clock Input
The LTC1740 only uses the rising edge of the CLK pin for
internal timing, and CLK doesn’t necessarily need to have
a 50% duty cycle. For optimal AC performance the rise
time of the CLK should be less than 5ns. If the available
clock has a rise time slower than 5ns, it can be locally sped
up with a logic gate. The clock can be driven with 5V
CMOS, 3V CMOS or TTL logic levels.
APPLICATIO S I FOR ATIO
WU
UU
R2
1k
10k
1
F
1740 F11
+AIN
VSS
VIN
5V
–5V
LTC1740
5V
–AIN
SENSE
VREF
10k
24k
100
R1
50k
Figure 11. Offset and Full-Scale Adjust Circuit
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