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參數(shù)資料
| 型號： | LTC1749CFW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 80MSPS SMPL 48TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,800 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.69W |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
12
LTC1749
1749f
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third stage, resulting in a third stage residue
that is sent to the fourth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC1749
CMOS differential sample-and-hold. The differential ana-
log inputs are sampled directly onto sampling capacitors
(CSAMPLE) through NMOS switches. This direct capacitor
sampling results in lowest possible noise for a given
sampling capacitor size. The capacitors shown attached to
each input (CPARASITIC) are the summation of all other
capacitance associated with each input.
During the sample phase when ENC/ENC is low, the NMOS
switch connects the analog inputs to the sampling capaci-
tors and they charge to, and track the differential input
voltage. When ENC/ENC transitions from low to high the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC/ENC is high the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As
ENC/ENC transitions from high to low the inputs are
reconnected to the sampling capacitors to acquire a new
sample. Since the sampling capacitors still hold the previ-
ous sample, a charging glitch proportional to the change
in voltage between samples will be seen at this time. If the
change between the last sample and the new sample is
small the charging glitch seen at the input will be small. If
the input change is large, such as the change seen with
input frequencies near Nyquist, then a larger charging
glitch will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential drive
to achieve specified performance. Each input should swing
within the valid input range, around a common mode volt-
age of 2.0V. The VCM output pin (Pin 2) may be used to pro-
vide the common mode bias level. VCM can be tied directly
to the center tap of a transformer to set the DC input level
or as a reference level to an op amp differential driver cir-
cuit. The VCM pin must be bypassed to ground close to the
ADC with a 4.7
F or greater capacitor.
APPLICATIO S I FOR ATIO
WU
UU
Figure 2. Equivalent Input Circuit
CSAMPLE
3.5pF
RON
30
RON
30
VDD
LTC1749
AIN
+
1749 F02
CSAMPLE
3.5pF
BIAS
VDD
5V
AIN
–
ENC
2V
6k
2V
6k
CPARASITIC
2.4pF
CPARASITIC
1pF
CPARASITIC
1pF
CPARASITIC
2.4pF
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| LTC1749IFW#TR | 功能描述:IC ADC 12BIT 80MSPS SMPL 48TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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