參數(shù)資料
型號(hào): LTC1750CFW
廠商: Linear Technology
文件頁(yè)數(shù): 12/20頁(yè)
文件大小: 0K
描述: IC ADC 14BIT 80MSPS SMPL 48TSSOP
標(biāo)準(zhǔn)包裝: 39
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.69W
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 管件
輸入數(shù)目和類型: 2 個(gè)單端,雙極;1 個(gè)差分,雙極
2
LTC1750
1750f
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
q
14
Bits
Integral Linearity Error
(Note 6)
– 3
±0.75
3
LSB
Differential Linearity Error
q
–1
±0.5
1.5
LSB
Offset Error
(Note 7) External Reference (VSENSE = 1.125V, PGA = 0)
–35
±835
mV
Gain Error
External Reference (VSENSE = 1.125V, PGA = 0)
–3.5
±1
3.5
%FS
Full-Scale Tempco
Internal Reference
±40
ppm/
°C
External Reference (VSENSE = 1.125V)
±20
ppm/
°C
Offset Tempco
±20
V/°C
Input Referred Noise (Transition Noise)
VSENSE = 1.125V, PGA = 0
0.92
LSBRMS
ORDER PART
NUMBER
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ............................................. 5.5V
Analog Input Voltage (Note 3) .... – 0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4) ..... – 0.3V to (VDD + 0.3V)
Digital Output Voltage ................. – 0.3V to (VDD + 0.3V)
OGND Voltage .............................................. – 0.3V to 1V
Power Dissipation ............................................ 2000mW
Operating Temperature Range
LTC1750C ............................................... 0
°C to 70°C
LTC1750I ............................................ – 40
°C to 85°C
Storage Temperature Range ................. – 65
°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300
°C
LTC1750CFW
LTC1750IFW
TJMAX = 150°C, θJA = 35°C/W
The q indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
W
U
CO VERTER CHARACTERISTICS
U
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN
Analog Input Range (Note 8)
4.75V
≤ VDD ≤ 5.25V
q
±0.7 to ±1.125
V
IIN
Analog Input Leakage Current
0 < AIN+, AIN– < VDD
q
–1
1
A
CIN
Analog Input Capacitance
Sample Mode ENC < ENC
6.9
pF
Hold Mode ENC > ENC
2.4
pF
tACQ
Sample-and-Hold Acquisition Time
q
56
ns
tAP
Sample-and-Hold Acquisition Delay Time
0
ns
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
0.12
psRMS
CMRR
Analog Input Common Mode Rejection Ratio
1.5V < (AIN– = AIN+) < 3V
80
dB
The q indicates specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
A ALOG I PUT
U
Consult LTC Marketing for parts specified with wider operating temperature ranges.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TOP VIEW
FW PACKAGE
48-LEAD PLASTIC TSSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SENSE
VCM
GND
AIN
+
AIN
GND
VDD
GND
REFLB
REFHA
GND
REFLA
REFHB
GND
VDD
GND
VDD
GND
MSBINV
ENC
OF
OGND
D13
D12
D11
OVDD
D10
D9
D8
D7
OGND
GND
D6
D5
D4
OVDD
D3
D2
D1
D0
OGND
CLKOUT
PGA
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