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參數(shù)資料
| 型號： | LTC1750CFW |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 80MSPS SMPL 48TSSOP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.69W |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
15
LTC1750
1750f
Input Range
The LTC1750 performance may be optimized by adjusting
the ADC’s input range to meet the requirements of the
application. For lower input frequency applications
(<80MHz), the highest input range of
±1.125V(2.25V)will
provide the best SNR while maintaining excellent SFDR.
For higher input frequencies (>80MHz), a lower input
range will provide better SFDR performance with a reduc-
tion in SNR.
The input range of the ADC is determined as
±VREF/APGA,
where VREF is the reference voltage (described in the
Reference Operation section) and APGA is the effective
APPLICATIO S I FOR ATIO
WU
UU
PGA gain. Table 1 shows the input range of the ADC versus
the state of the two pins, PGA and SENSE.
Driving the Encode Inputs
The noise performance of the LTC1750 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
The encode inputs have a common mode range of 1.8V to
VDD. Each input may be driven from ground to VDD for
single-ended drive.
VCM
SENSE
2V
1V
4.7
F
10k
1
F
10k
1750 F06a
LTC1750
VCM
SENSE
2V
5V
2.5k
6
4
1, 2
4.7
F
1
F
1
F
10k
0.1
F
1750 F06b
LTC1750
LT1790-1.25
Figure 6a. 2V Range ADC
Figure 6b. 2V Range ADC with External Reference
Table 1
PGA
VSENSE
INPUT RANGE
COMMENTS
0= VDD
2.25VP-P Differential
Best Noise, SNR = 75.5dB. Good SFDR, >82dB Up to 100MHz
1= VDD
1.35VP-P Differential
Improved High Frequency Distortion. SNR = 73dB. SFDR > 80dB Up to 250MHz
0
= GND
1.4VP-P Differential
Reduced Internal Reference Mode with PGA = 0. Provides Similar Input Range as
VSENSE = VDD and PGA = 0 But with Worse Noise. SNR = 71.4dB
1
= GND
0.84VP-P Differential
Smallest Possible Input Span. Useful for Improved Distortion at Very High
Frequencies, But with Reduced Noise Performance. SNR = 69dB
0
0.7V < VSENSE < 1.125V
2
× VSENSE
Adjustable Input Range with Better Noise Performance. SNR = 75.5dB with
Peak-to-Peak Differential
VSENSE = 1.125V, SNR = 71.4dB with VSENSE = 0.7V
1
0.7V < VSENSE < 1.125V
1.2
× VSENSE
Adjustable Input Range with Better High Frequency Distortion. SNR = 73dB with
Peak-to-Peak Differential
VSENSE = 1.125V, SNR = 69dB with VSENSE = 0.7V
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