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參數(shù)資料
| 型號： | LTC1773 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Synchronous Step-Down Regulator Controller(同步步降穩(wěn)壓器) |
| 中文描述： | 同步降壓穩(wěn)壓控制器（同步步降穩(wěn)壓器） |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 274K |
| 代理商： | LTC1773 |
LTC1773
9
commonly used for design because even significant de-
viations do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
C
OUT
Selection
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (
V
OUT
) is determined by:
V
I ESR
fC
OUT
OUT
+
1
8
where f = operating frequency, C
OUT
= output capacitance
and
I
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since
I
L
increases
with input voltage. With
I
L
= 0.4I
OUT(MAX)
and allowing
for 2/3 of the ripple due to ESR, the output ripple will be
less than 50mV at max V
IN
assuming:
C
OUT
required ESR < 2 R
SENSE
C
OUT
> 1/(8fR
SENSE
)
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran-
tees that the output voltage does not significantly dis-
charge during the operating frequency period due to ripple
current. The choice of using smaller output capacitance
increases the ripple voltage due to the discharging term
but can be compensated for by using capacitors of very
low ESR to maintain the ripple voltage at or below 50mV.
The I
TH
pin OPTI-LOOP compensation components can be
optimized to provide stable, high performance transient
response regardless of the output capacitors selected.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest ESR/size
P
V
V
V
I
R
)
SYNC
IN
OUT
IN
MAX
DS ON
=
(
)
+
(
)
–
2
1
δ
where
δ
is the temperature dependency of R
DS(ON)
and K
is a constant inversely related to the gate drive current.
Both MOSFETs have I
2
R losses while the topside P-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. The synchronous
MOSFET losses are greatest at high input voltage or during
a short-circuit when the duty cycle in this switch is nearly
100%.
The term (1 +
δ
) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs temperature curve, but
δ
= 0.005/
°
C can be used as an approximation for low
voltage MOSFETs. C
RSS
is usually specified in the MOSFET
characteristics. The constant K = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.
A Schottky diode can be placed in parallel with the syn-
chronous MOSFET to improve efficiency. It conducts
during the dead-time between the conduction of the two
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on and storing charge
during the dead-time, which could cost as much as 1% in
efficiency. A 1A Schottky is generally a good size for 5A to
8A regulators due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance. The diode may be omit-
ted if the efficiency loss can be tolerated.
C
IN
Selection
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
C
required I
I
V
V
V
V
IN
RMS
MAX
OUT
IN
OUT
IN
–
(
)
[
]
12
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is
APPLICATIO
S I
FOR
ATIO
U
W
U
U
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