- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2005 > LTC1851CFW (Linear Technology)IC ADC 12BIT 1.25MSPS 48-TSSOP PDF資料下載
參數(shù)資料
| 型號： | LTC1851CFW |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 1.25MSPS 48-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁面： | 1347 (CN2011-ZH PDF) |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
11
LTC1850/LTC1851
18501f
D9/S0 (Pin 23, LTC1851): Three-State Digital Data Out-
puts. Active when RD is low. Following a conversion, bit 9
of the present conversion is available on this pin. In
Readback mode, the end of sequence bit of the current
sequencer location (S0) is available on this pin. The output
swings between OVDD and OGND.
D6 to D0 (Pins 24 to 30, LTC1850): Three-State Digital
Data Outputs. Active when RD is low. The outputs swing
between OVDD and OGND.
D8 to D0 (Pins 24 to 32, LTC1851): Three-State Digital
Data Outputs. Active when RD is low. The outputs swing
between OVDD and OGND.
NC (Pins 31, 32, LTC1850): No Connect. There is no
internal connection to these pins.
BUSY (Pin 33): Converter Busy Output. The BUSY output
has two functions. At the start of a conversion, BUSY will
go low and remain low until the conversion is completed.
The rising edge may be used to latch the output data. BUSY
will also go low while the part is in Program/Readback
mode (M1 high, M0 low) and remain low until M0 is
brought back high. The output swings between OVDD and
OGND.
OGND (Pin 34): Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OVDD (Pin 35): Digital Data Output Supply. Normally tied
to 5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10
F tantalum in parallel with 0.1F ceramic
or 10
F ceramic. See Table 5.
M0 (Pin 36): Mode Select Pin 0. Used in conjunction with
M1 to select operating mode. See Table 5
PGA (Pin 37): Gain Select Input. A high logic level selects
gain = 1, a low logic level selects gain = 2.
UU
U
PI FU CTIO S
UNI/BIP (Pin 38): Unipolar/Bipolar Select Input. Logic low
selects a unipolar input span, a high logic level selects a
bipolar input span.
A0 to A2 (Pins 39 to 41): MUX Address Input Pins.
DIFF (Pin 42): Single-Ended/Differential Select Input. A
low logic level selects single-ended mode, a high logic
level selects differential mode.
WR (Pin 43): Write Input. In Direct Address mode, WR low
enables the MUX address and configuration input pins
(Pins 37 to 42). WR can be tied low or the rising edge of
WR can be used to latch the data. In Program mode, WR
is used to program the sequencer. WR low enables the
MUX address and configuration input pins (Pins 37 to 42).
The rising edge of WR latches the data and increments the
counter to the next sequencer location.
RD (Pin 44): Read Input. During normal operation, RD
enables the output drivers when CS is low. In Readback
mode (M1 high, M0 low), RD going low reads the current
sequencer location, RD high advances to the next sequencer
location.
CONVST (Pin 45): Conversion Start Input. This active low
signal starts a conversion on its falling edge.
CS (Pin 46): Chip Select Input. The chip select input must
be low for the ADC to recognize the CONVST and RD
inputs. If SHDN is low, a low logic level on CS selects Nap
mode; a high logic level on CS selects Sleep mode.
SHDN (Pin 47): Power Shutdown Input. A low logic level
will invoke the Shutdown mode selected by the CS pin. CS
low selects Nap mode, CS high selects Sleep mode. Tie
high if unused.
M1 (Pin 48): Mode Select Pin 1. Used in conjunction with
M0 to select operating mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC1853IFW#TRPBF | IC A/D CONV 8CH 12BIT 48-TSSOP |
| LTC1856IG#PBF | IC ADC 16BIT 100KSPS 28-SSOP |
| LTC1859IG#TRPBF | IC A/D CONV 8CH 16BIT 28-SSOP |
| LTC1867AIGN#TRPBF | IC ADC 16BIT 8CH 200KSPS 16SSOP |
| LTC1867LCGN#PBF | IC ADC 16BIT 8CH 175KSPS 16SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC1851CFW#PBF | 功能描述:IC ADC 12BIT 1.25MSPS 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| LTC1851CFW#TR | 功能描述:IC ADC 12BIT 1.25MSPS 48-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| LTC1851CFW#TRPBF | 功能描述:IC ADC 12BIT 1.25MSPS 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| LTC1851CFWPBF | 制造商:Linear Technology 功能描述:ADC,LTC1851 12bit 1.25MSPS 8 ch TSSOP |
| LTC1851IFW | 功能描述:IC ADC 12BIT 1.25MSPS 48-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。