參數(shù)資料
型號: LTC1851CFW
廠商: Linear Technology
文件頁數(shù): 6/28頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 1.25MSPS 48-TSSOP
標(biāo)準(zhǔn)包裝: 39
位數(shù): 12
采樣率(每秒): 1.25M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 50mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 管件
輸入數(shù)目和類型: 8 個(gè)單端,單極;8 個(gè)單端,雙極;4 個(gè)差分,單極;4 個(gè)差分,雙極
產(chǎn)品目錄頁面: 1347 (CN2011-ZH PDF)
14
LTC1850/LTC1851
18501f
APPLICATIO S I FOR ATIO
WU
UU
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa
± nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include (fa
±fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
IMD fa
fb
Log
Amplitude at fa
fb
Amplitude at fa
±
()=
±
()
20
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB for the LTC1851 (11
effective bits) or 56dB for the LTC1850 (9 effective bits).
The LTC1850/LTC1851 have been designed to optimize
input bandwidth, allowing the ADC to undersample input
signals with frequencies above the converter’s Nyquist
frequency. The noise floor stays very low at high frequen-
cies; S/(N + D) becomes dominated by distortion at
frequencies far beyond Nyquist.
ANALOG INPUT MULTIPLEXER
The analog input multiplexer is controlled using the single-
ended/differential pin (DIFF), three MUX address pins (A2,
A1, A0), the unipolar/bipolar pin (UNI/BIP) and the gain
select pin (PGA). The single-ended/differential pin (DIFF)
allows the user to configure the MUX as eight single-
ended channels relative to the analog input common pin
(COM) when DIFF is low or as four differential pairs (CH0
and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) when
DIFF is high. The channels (and polarity in the differential
case) are selected using the MUX address inputs as shown
in Table 1. Unused inputs (including the COM in the
differential case) should be grounded to prevent noise
coupling.
Table 1. Multiplexer Address Table
MUX ADDRESS
SINGLE-ENDED CHANNEL SELECTION
DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
00
0
+
00
0
1
+
00
1
0
+
00
1
+
01
0
+
01
0
1
+
01
1
0
+
01
1
+
MUX ADDRESS
DIFFERENTIAL CHANNEL SELECTION
DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
10
0
+
*
10
0
1
+
*
10
1
0
+
*
10
1
+
*
11
0
+
*
11
0
1
+
*
11
1
0
+
*
11
1
+
*
*Not used in differential mode. Connect to GND.
In addition to selecting the MUX channel, the LTC1850/
LTC1851 also allows the user to select between two gains
and unipolar or bipolar inputs for a total of four input
spans. PGA high selects a gain of 1 (the input span is equal
to the voltage on REFCOMP). PGA low selects a gain of 2
where the input span is equal to half of the voltage on
REFCOMP. UNI/BIP low selects a unipolar input span,
UNI/BIP high selects a bipolar input span. Table 2 summa-
rizes the possible input spans.
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