參數(shù)資料
型號: LTC2141IUP-14#PBF
廠商: Linear Technology
文件頁數(shù): 22/38頁
文件大?。?/td> 0K
描述: IC ADC DUAL 14BIT 40 MSPS 64-QFN
標準包裝: 40
位數(shù): 14
采樣率(每秒): 40M
數(shù)據(jù)接口: 并聯(lián),串行,SPI
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 218mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-QFN(9x9)
包裝: 管件
輸入數(shù)目和類型: 2 個差分
配用: DC890B-ND - BOARD USB DATA COLLECTION
29
21421014fa
LTC2142-14/
LTC2141-14/LTC2140-14
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
D5
D4
D3
D2
D1
D0
RESET
XXXXXX
X
Bit 7
RESET
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. This Bit Is
Automatically Set Back to Zero at the end of the SPI write command. The Reset Register Is Write-only. Data Readback from the Reset
Register will Be Random.
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXX
PWROFF1
PWROFF0
Bits 7-2
Unused, Don’t Care Bits.
Bits 1-0
PWROFF1:PWROFF0
Power Down Control Bits
00 = Normal Operation
01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode
10 = Channel 1 and Channel 2 in Nap Mode
11 = Sleep Mode
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
XXXX
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, Don’t Care Bits.
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUTDelayed by 45° (Clock Period 1/8)
10 = CLKOUT+/CLKOUTDelayed by 90° (Clock Period 1/4)
11 = CLKOUT+/CLKOUTDelayed by 135° (Clock Period 3/8)
Note: If the CLKOUT Phase Delay Feature Is Used, the Clock Duty Cycle Stabilizer Must Also Be Turned On
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
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