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參數(shù)資料
| 型號： | LTC2145IUP-14#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 21/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 14BIT 125MSPS 64-QFN |
| 標準包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián)，串行，SPI |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 360mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分 |
| 配用： | DC890B-ND - BOARD USB DATA COLLECTION |
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LTC2145-14/
LTC2144-14/LTC2143-14
28
21454314fa
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become a
serial interface that program the A/D mode control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required. If
serial data is only written and read back is not needed, then
SDO can be left floating and no pull-up resistor is needed.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
GROUNDING AND BYPASSING
The LTC2145-14/LTC2144-14/LTC2143-14 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass
capacitors must be located as close to the pins as pos-
sible. Size 0402 ceramic capacitors are recommended. The
traces connecting the pins and bypass capacitors must
be kept short and should be made as wide as possible.
Of particular importance is the capacitor between REFH
and REFL. This capacitor should be on the same side of
the circuit board as the A/D, and as close to the device
as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC2145-14/LTC2144-
14/LTC2143-14 is transferred from the die through the
bottom-side exposed pad and package leads onto the
printed circuit board. For good electrical and thermal
performance, the exposed pad must be soldered to a large
grounded pad on the PC board. This pad should be con-
nected to the internal ground planes by an array of vias.
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