參數(shù)資料
型號(hào)： LTC2155CUP-14#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64
文件頁數(shù)： 11/32頁
文件大?。?/td> 647K
代理商： LTC2155CUP-14#PBF
19
21576514f
LTC2157-14/
LTC2156-14/LTC2155-14
APPLICATIONS INFORMATION
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. The duty cycle
stabilizer is enabled via SPI Register A2 (see Table 3) or
by CS in parallel programming mode.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. In
this cases care should be taken to make the clock a 50%
(± 5%) duty cycle.
DIGITAL OUTPUTS
The digital outputs are double data rate LVDS signals. Two
data bits are multiplexed and output on each differential
Figure 9. Sinusoidal Encode Drive
output pair. There are seven LVDS output pairs for chan-
nel A (DA0_1+/DA0_1– through DA12_13–/DA12_13+)
and seven pairs for channel B (DB0_1+/DB0_1– through
DB12_13–/DB12_13+). Overflow (OF+/OF–) and the data
output clock (CLKOUT+/CLKOUT–) each have an LVDS
output pair. Note that overflow for both channels is mul-
tiplexed onto the OF+/OF– output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage.
Anexternal100Ωdifferentialterminationresistorisrequired
for each LVDS output pair. The termination resistors should
be located as close as possible to the LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
LTC2157-14
VDD
21576514 F09
1.2V
10k
50Ω
100Ω
50Ω
0.1μF
T1: MACOM
ETC1-1-13
Figure 10. PECL or LVDS Encode Drive
VDD
LTC2157-14
PECL OR
LVDS INPUT
21576514 F10
1.2V
10k
100Ω
0.1μF
ENC+
ENC–
相關(guān)PDF資料
PDF描述
LTC2156CUP-14#TRPBF 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2155CUP-14#TRPBF 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2156IUP-14#TRPBF 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2156CUP-14#PBF 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2157IUP-14#TRPBF 2-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
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