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參數(shù)資料
型號： LTC2175IUKG-14#TRPBF
廠商： Linear Technology
文件頁數(shù)： 23/34頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 125MSPS QUAD 52QFN
標準包裝： 2,000
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： Serial LVDS
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 646mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 52-WFQFN 裸露焊盤
供應商設備封裝： 52-QFN（7x8）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 Differential; 2 Single-Ended
配用： DC1371A-ND - BOARD USB DATA ACQUISITION HS
3
21754314fa
LTC2175-14/
LTC2174-14/LTC2173-14
converTer characTerisTics The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
LTC2175-14
LTC2174-14
LTC2173-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Resolution (No Missing Codes)
l
14
Bits
Integral Linearity Error
Differential Analog Input (Note 6) l –4.1
±1.2
4.1
–3.25
±1
3.25 –2.75
±1
2.75
LSB
Differential Linearity Error
Differential Analog Input
l
–0.9
±0.3
0.9
–0.8
±0.3
0.8
–0.8
±0.3
0.8
LSB
Offset Error
(Note 7)
l
–12
±3
12
–12
±3
12
–12
±3
12
mV
Gain Error
Internal Reference
External Reference
l
–2.6
–1.3
0
–2.6
–1.3
0
–2.6
–1.3
0
%FS
Offset Drift
±20
V/°C
Full-Scale Drift
Internal Reference
External Reference
±35
±25
±35
±25
±35
±25
ppm/°C
Gain Matching
External Reference
±0.2
%FS
Offset Matching
±3
mV
Transition Noise
External Reference
1.2
LSBRMS
analog inpuT The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
1 to 2
VP-P
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Analog Input (Note 8) l VCM – 100mV
VCM
VCM + 100mV
V
VSENSE
External Voltage Reference Applied to SENSE External Reference Mode
l
0.625
1.250
1.300
V
IINCM
Analog Input Common Mode Current
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
155
130
100
A
IIN1
Analog Input Leakage Current No Encode
0 < AIN+, AIN– < VDD,
l
–1
1
A
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–3
3
A
IIN3
SENSE Input Leakage Current
0.625 < SENSE < 1.3V
l
–6
6
A
tAP
Sample-and-Hold Acquisition Delay Time
0
ns
tJITTER
Sample-and-Hold Acquisition Delay Jitter
0.15
psRMS
CMRR
Analog Input Common Mode Rejection Ratio
80
dB
BW-3B
Full-Power Bandwidth
Figure 6 Test Circuit
800
MHz
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