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參數(shù)資料
型號： LTC2175IUKG-14#TRPBF
廠商： Linear Technology
文件頁數(shù)： 31/34頁
文件大小： 0K
描述： IC ADC 14BIT 125MSPS QUAD 52QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： Serial LVDS
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 646mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 52-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 52-QFN（7x8）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 Differential; 2 Single-Ended
配用： DC1371A-ND - BOARD USB DATA ACQUISITION HS
LTC2175-14/
LTC2174-14/LTC2173-14
6
21754314fa
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
LTC2175-14
LTC2174-14
LTC2173-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
IVDD
Analog Supply Current
Sine Wave Input
l
283
305
224
243
184
200
mA
IOVDD
Digital Supply Current
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
27
49
31
54
26
48
31
53
25
47
29
52
mA
PDISS
Power Dissipation
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
558
598
605
646
450
490
493
533
376
416
412
454
mW
PSLEEP
Sleep Mode Power
1
mW
PNAP
Nap Mode Power
85
mW
PDIFFCLK Power Increase With Differential Encode Mode Enabled
(No Increase for Sleep Mode)
20
mW
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
LTC2175-14
LTC2174-14
LTC2173-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
fS
Sampling Frequency
(Notes 10,11)
l
5
125
5
105
5
80
MHz
tENCL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.8
2
4
100
4.52
2
4.76
100
5.93
2
6.25
100
ns
tENCH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.8
2
4
100
4.52
2
4.76
100
5.93
2
6.25
100
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
ns
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER
Serial Data Bit Period
2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
1/(8 fS)
1/(7 fS)
1/(6 fS)
1/(16 fS)
1/(14 fS)
1/(12 fS)
s
tFRAME
FR to DCO Delay
(Note 8)
l
0.35 tSER
0.5 tSER
0.65 tSER
s
tDATA
DATA to DCO Delay
(Note 8)
l
0.35 tSER
0.5 tSER
0.65 tSER
s
tPD
Propagation Delay
(Note 8)
l
0.7n + 2 tSER 1.1n + 2 tSER 1.5n + 2 tSER
s
tR
Output Rise Time
Data, DCO, FR, 20% to 80%
0.17
ns
tF
Output Fall Time
Data, DCO, FR, 20% to 80%
0.17
ns
DCO Cycle-Cycle Jitter
tSER = 1ns
60
psP-P
Pipeline Latency
6
Cycles
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