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參數(shù)資料
| 型號： | LTC2221CUP#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12-BIT 135MSPS 64-QFN |
| 標準包裝： | 40 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 135M |
| 數(shù)據接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 931mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN（9x9） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，雙極; 1 個差分，雙極 |
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LTC2220/LTC2221
13
22201fa
UU
U
PI FU CTIO S
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. Connecting SENSE to VDD selects the internal
reference and a
±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of
±VSENSE. ±1V is the largest valid
input range.
VCM (Pin 60): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2
F ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
(LVDS Mode)
AIN+ (Pins 1, 2): Positive Differential Analog Input.
AIN– (Pins 3, 4): Negative Differential Analog Input.
REFHA (Pins 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1
F ceramic chip capacitor, to Pins 11, 12
with a 2.2
F ceramic capacitor and to ground with 1F
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,
6 with 0.1
F ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1
F ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1
F ceramic chip capacitor, to Pins 5, 6
with a 2.2
F ceramic capacitor and to ground with 1F
ceramic capacitor.
VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to
GND with 0.1
F ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC+ (Pin 17): Encode Input. Conversion starts on the
positive edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1
F
ceramic for single-ended ENCODE signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin
function.
D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29,
30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52,
53, 54): LVDS Digital Outputs. All LVDS outputs require
differential 100
termination resistors at the LVDS re-
ceiver. D11–/D11+ is the MSB.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output
Drivers. Bypass to ground with 0.1
F ceramic chip
capacitor.
CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid
Output. Latch data on rising edge of CLKOUT–, falling edge
of CLKOUT+.
OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output.
High when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3VDD selects demux CMOS mode with simulta-
neous update. Connecting LVDS to 2/3VDD selects demux
CMOS mode with interleaved update. Connecting LVDS to
VDD selects LVDS mode.
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