參數(shù)資料
型號: LTC2221CUP#PBF
廠商: Linear Technology
文件頁數(shù): 6/32頁
文件大?。?/td> 0K
描述: IC ADC 12-BIT 135MSPS 64-QFN
標準包裝: 40
位數(shù): 12
采樣率(每秒): 135M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 931mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-QFN(9x9)
包裝: 管件
輸入數(shù)目和類型: 1 個單端,雙極; 1 個差分,雙極
LTC2220/LTC2221
14
22201fa
UU
U
PI FU CTIO S
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3VDD selects offset
binary output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to 2/3VDD selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. Connecting SENSE to VDD selects the internal
reference and a
±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of
±VSENSE. ±1V is the largest valid
input range.
VCM (Pin 60): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2
F ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
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