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參數(shù)資料
| 型號： | LTC2229CUH#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12-BIT 80MSPS 3V 32-QFN |
| 標準包裝： | 73 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 246mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，雙極; 1 個差分，雙極 |
| 產品目錄頁面： | 1349 (CN2011-ZH PDF) |
LTC2229
13
2229fa
APPLICATIO S I FOR ATIO
WU
U
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing
±0.5V for
the 2V range or
±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin (Pin
31) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2
F or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2229 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and reactance can
influence SFDR. At the falling edge of CLK, the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when CLK rises, holding the sampled input on
the sampling capacitor. Ideally the input circuitry should
be fast enough to fully charge the sampling capacitor
during the sampling period 1/(2FENCODE); however, this is
not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100
or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2229 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100
for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
Figure 4. Differential Drive with an Amplifier
25
25
25
25
0.1
F
AIN
+
AIN
–
12pF
2.2
F
VCM
LTC2229
ANALOG
INPUT
0.1
FT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2229 F03
25
25
12pF
2.2
F
VCM
LTC2229
2229 F04
–
+
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
AIN
+
AIN
–
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