參數(shù)資料
型號(hào)： LTC2229CUH#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 8/24頁(yè)
文件大小： 0K
描述： IC ADC 12-BIT 80MSPS 3V 32-QFN
標(biāo)準(zhǔn)包裝： 73
位數(shù)： 12
采樣率（每秒）： 80M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 246mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x5）
包裝： 管件
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，雙極; 1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 1349 (CN2011-ZH PDF)
LTC2229
16
2229fa
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to ground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a capaci-
tor at the input may result in peaking, and depending on
transmission line length may require a 10
to 20 ohm
series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mecha-
nism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2229 is 80Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (
±5%) duty cycle. Each half cycle must have
at least 5.9ns for the ADC internal circuitry to have enough
settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To use
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2229 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2229 is 1Msps.
APPLICATIO S I FOR ATIO
WU
UU
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
Figure 13. LVDS or PECL CLK Drive Using a Transformer
CLK
100
0.1
F
4.7
F
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
2229 F12
LTC2229
CLK
5pF-30pF
ETC1-1T
0.1
F
VCM
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
2229 F13
LTC2229
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