- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10071 > LTC2230IUP#TRPBF (Linear Technology)IC ADC 10BIT 170MSPS 64-QFN PDF資料下載
參數(shù)資料
| 型號： | LTC2230IUP#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 170MSPS 64-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.18W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極; 1 個差分，雙極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
LTC2230/LTC2231
19
22301fb
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third and fourth stages, resulting in a fourth
stage residue that is sent to the fifth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2230/
LTC2231 CMOS differential sample-and-hold. The analog
inputs are connected to the sampling capacitors (CSAMPLE)
through NMOS transistors. The capacitors shown at-
tached to each input (CPARASITIC) are the summation of all
other capacitance associated with each input.
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
When ENC transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when ENC is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
CSAMPLE
1.6pF
VDD
LTC2230/LTC2231
AIN
+
22201 F02
CSAMPLE
1.6pF
VDD
AIN
–
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1pF
CPARASITIC
1pF
15
Ω
15
Ω
Figure 2. Equivalent Input Circuit
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.6V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing
±0.5V for
the 2V range or
±0.25V for the 1V range, around a
common mode voltage of 1.6V. The VCM output pin (Pin
APPLICATIO S I FOR ATIO
WU
UU
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS3101R20-21P | CONN RCPT 9POS PANEL MNT W/PINS |
| MS3102A20-29SZ | CONN RCPT 17POS BOX MNT W/SCKT |
| IDT72V801L20PF8 | IC SYNC FIFO 256X9 20NS 64QFP |
| IDT7206L50J | IC FIFO 8192X18 50NS 32PLCC |
| IDT7206L50P | IC FIFO 8192X18 50NS 28DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2230UP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit,170Msps/135Msps ADCs |
| LTC2231 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit,170Msps/135Msps ADCs |
| LTC2231CUP | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit,170Msps/135Msps ADCs |
| LTC2231CUP#PBF | 功能描述:IC ADC 10BIT 135MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2231CUP#TRPBF | 功能描述:IC ADC 10BIT 135MSPS 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。