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參數(shù)資料
| 型號： | LTC2259CUJ-14#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/34頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 80MSPS 40-QFN |
| 產(chǎn)品培訓(xùn)模塊： | LTC2262 - Ultra Low Power High Speed ADCs |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián)，串行，SPI |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 105mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-QFN（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分 |
| 配用： | DC890B-ND - BOARD USB DATA COLLECTION |
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LTC2261-14
LTC2260-14/LTC2259-14
16
226114fc
For more information www.linear.com/LTC2261-14
pin FuncTions
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0 to D13 (Pins 17-24, 29-34): Digital Outputs. D13 is
the MSB.
CLKOUT– (Pin 27): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DNC (Pin 35): Do not connect this pin.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE-DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0_1 to D12_13 (Pins 18, 20, 22, 24, 30, 32, 34): Double-
Data Rate Digital Outputs. Two data bits are multiplexed onto
eachoutputpin.Theevendatabits(D0,D2,D4,D6,D8,D10,
D12) appear when CLKOUT+ is low. The odd data bits (D1,
D3, D5, D7, D9, D11, D13) appear when CLKOUT+ is high.
CLKOUT– (Pin 27): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
ing edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 19, 21, 23, 29, 31, 33, 35): Do not con-
nect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE-DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100 Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1–/D0_1+ to D12_13–/D12_13+ (Pins 17/18, 19/20,
21/22, 23/24, 29/30, 31/32, 33/34): Double-Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (D0, D2, D4,
D6, D8, D10, D12) appear when CLKOUT+ is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–/OF+ (Pins 35/36): Over/Under Flow Digital Output.
OF+ is high when an overflow or underflow has occurred.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2259CUJ-16 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
| LTC2259CUJ-16#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 80Msps 16-bit Parallel/LVDS 40-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 80MSPS 40QFN 制造商:Linear Technology 功能描述:IC ADC 16BIT 80MSPS QFN-40 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 80MSPS, QFN-40; Resolution (Bits):16bit; Sampling Rate:80MSPS; Supply Voltage Type:Single; Supply Voltage Min:1.7V; Supply Voltage Max:1.9V; Supply Current:49.2mA; Digital IC Case Style:QFN; No. of Pins:40; INL :4LSB;RoHS Compliant: Yes |
| LTC2259CUJ-16#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 80Msps 16-bit Parallel/LVDS 40-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 80MSPS 40QFN |
| LTC2259CUJ-16PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
| LTC2259CUJ-16TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
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