For more information www.linear.com/LTC2262-12 POWER REQUIREMENT" />
參數(shù)資料
型號(hào): LTC2262CUJ-12#TRPBF
廠商: Linear Technology
文件頁數(shù): 25/28頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 150MSPS 40-QFN
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
采樣率(每秒): 150M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 146mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分
配用: DC890B-ND - BOARD USB DATA COLLECTION
LTC2262-12
6
226212fc
For more information www.linear.com/LTC2262-12
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
(Note 10)
l
1
150
MHz
tL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.17
2.0
3.33
500
ns
tH
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.17
2.0
3.33
500
ns
tAP
Sample-and-Hold Acquisition Delay
Time
0
ns
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.7
3.1
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.4
2.6
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
Full Data Rate Mode
Double Data Rate Mode
5.0
5.5
Cycles
Digital Data Outputs (LVDS Mode)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.8
3.2
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.5
2.7
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
5.5
Cycles
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LVDS Output Mode
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.9
V
IVDD
Analog Supply Current
Sine Wave Input
l
86.3
99.2
mA
IOVDD
Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
18.8
36.7
21
40
mA
PDISS
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
189
221
217
251
mW
All Output Modes
PSLEEP
Sleep Mode Power
0.5
mW
PNAP
Nap Mode Power
9
mW
PDIFFCLK
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
10
mW
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