For more information www.linear.com/LTC2262-12 SYMBOL PARAMETER CONDITIONS MIN TY" />
參數(shù)資料
型號(hào)： LTC2262CUJ-12#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 26/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 150MSPS 40-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
采樣率（每秒）： 150M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 146mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN（6x6）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分
配用： DC890B-ND - BOARD USB DATA COLLECTION
LTC2262-12
7
226212fc
For more information www.linear.com/LTC2262-12
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SPI Port Timing (Note 8)
tSCK
SCK Period
Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
40
250
ns
tS
CS to SCK Setup Time
l
5
ns
tH
SCK to CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK Falling to SDO Valid
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
125
ns
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 150MHz, LVDS outputs with
internal termination disabled, differential ENC+/ENC– = 2VP-P sine wave,
input range = 2VP-P with differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = 1.8V, fSAMPLE = 150MHz, ENC+ = single-ended 1.8V square
wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on
each digital output unless otherwise noted.
Note 10: Recommended operating conditions.
TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tH
tD
tC
tL
N – 5
N – 4
N – 3
N – 2
N – 1
tAP
N + 1
N + 2
N + 4
N + 3
N
ANALOG
INPUT
ENC–
ENC+
CLKOUT+
CLKOUT–
D0-D11, OF
226212 TD01
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