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參數(shù)資料
| 型號： | LTC2285CUP#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 14BIT 125MSPS 64QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 915mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極; 2 個差分, 雙極 |
LTC2285
16
2285fb
APPLICATIONS INFORMATION
Figure 11. Sinusoidal Single-Ended CLK Drive
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
Figure 13. LVDS or PECL CLK Drive Using a Transformer
The noise performance of the LTC2285 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
In applications where jitter is critical, such as when digi-
tizing high input frequencies, use as large an amplitude
as possible. Also, if the ADC is clocked with a sinusoidal
signal, lter the CLK signal to reduce wideband noise and
distortion products generated by the source.
It is recommended that CLKA and CLKB are shorted to-
gether and driven by the same clock source. If a small time
delay is desired between when the two channels sample
the analog inputs, CLKA and CLKB can be driven by two
different signals. If this delay exceeds 1ns, the performance
of the part may degrade. CLKA and CLKB should not be
driven by asynchronous signals.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bear-
ing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full scale, the use of these translators will have
a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to ground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a ca-
pacitor at the input may result in peaking, and depending
on transmission line length may require a 10Ω to 20Ω
ohm series resistor to act as both a low pass lter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2285 is 125Msps.
The lower limit of the LTC2285 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
CLK
50Ω
0.1μF
4.7μF
1k
FERRITE
BEAD
CLEAN
SUPPLY
SINUSOIDAL
CLOCK
INPUT
2285 F11
NC7SVU04
LTC2285
CLK
100Ω
0.1μF
4.7μF
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
2285 F12
LTC2285
CLK
5pF-30pF
ETC1-1T
0.1μF
VCM
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
2285 F13
LTC2285
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