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參數(shù)資料
| 型號： | LTC2285CUP#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 14BIT 125MSPS 64QFN |
| 標準包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 915mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極; 2 個差分, 雙極 |
LTC2285
17
2285fb
APPLICATIONS INFORMATION
small valued capacitors. Junction leakage will discharge
the capacitors. The specied minimum operating frequency
for the LTC2285 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures
high performance even if the input clock has a non
50% duty cycle. Using the clock duty cycle stabilizer is
recommended for most applications. To use the clock
duty cycle stabilizer, the MODE pin should be connected
to 1/3VDD or 2/3VDD using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40% to 60%
and the clock duty cycle stabilizer will maintain a constant
50% internal duty cycle. If the clock is turned off for a
long period of time, the duty cycle stabilizer circuit will
require a hundred clock cycles for the PLL to lock onto the
input clock.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overow bit. Note that
OF is high when an overow or underow has occurred
on either channel A or channel B.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D13 – D0
(Offset Binary)
D13 – D0
(2’s Complement)
>+1.000000V
+0.999878V
+0.999756V
1
0
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1110
+0.000122V
0.000000V
–0.000122V
–0.000244V
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.999878V
–1.000000V
<–1.000000V
0
1
00 0000 0000 0001
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single out-
put buffer. Each buffer is powered by OVDD and OGND,
isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2285 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. For full speed
operation the capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Figure 14. Digital Output Buffer
LTC2283
2283 F14
OVDD
VDD
0.1μF
43Ω
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Data Format
Using the MODE pin, the LTC2285 parallel digital output
can be selected for offset binary or 2’s complement format.
Connecting MODE to GND or 1/3VDD selects offset binary
output format. Connecting MODE to 2/3VDD or VDD selects
2’s complement output format. An external resistor divider
can be used to set the 1/3VDD or 2/3VDD logic values.
Table 2 shows the logic states for the MODE pin.
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