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參數(shù)資料
| 型號： | LTC2295IUP#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 14BIT 10MSPS 64QFN |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 10M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 138mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極; 2 個差分, 雙極 |
LTC2295
15
2295fa
APPLICATIO S I FOR ATIO
WU
UU
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 6. Each
ADC channel has an independent reference with its own
bypass capacitors. The two channels can be used with the
same or different input ranges.
Other voltage ranges between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 7. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1
F ceramic capacitor.
For the best channel matching, connect an external reference
to SENSEA and SENSEB.
Figure 7. 1.5V Range ADC
VCM
SENSE
1.5V
0.75V
2.2
F
12k
1
F
12k
2295 F7
LTC2295
Driving the Clock Input
The CLK inputs can be driven directly with a CMOS or TTL
level signal. A differential clock can also be used along with
a low jitter CMOS converter before the CLK pin (Figure 8).
Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter
The noise performance of the LTC2295 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this delay exceeds 1ns, the
performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5.8dB.
CLK
100
0.1
F
4.7
F
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
2295 F08
LTC2295
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| LTC2296CUP#PBF | 功能描述:IC ADC DUAL 14BIT 25MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| LTC2296CUP#TRPBF | 功能描述:IC ADC DUAL 14BIT 25MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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