參數(shù)資料
型號: LTC2400
廠商: Linear Technology Corporation
英文描述: 24-Bit uPower No Latency ADC in SO-8
中文描述: 24位uPower在ADC的無延遲蘇- 8
文件頁數(shù): 12/40頁
文件大?。?/td> 455K
代理商: LTC2400
12
LTC2400
APPLICATIO
S I
N
FOR
ATIO
U
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating a
new conversion cycle has been initiated. This bit serves as
EOC (Bit 31) for the next conversion cycle. Table 2 sum-
marizes the output data format.
As long as the voltage on the V
IN
pin is maintained within
the –0.3V to (V
CC
+ 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from –0.125 V
REF
to 1.125 V
REF
.
For input voltages
greater than 1.125 V
REF
, the conversion result is clamped
W
U
Table 2. LTC2400 Output Data Format
Bit 31
EOC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 30
DMY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 29
SIG
1
1
1
1
1
1
1
1
1
1
1/0**
0
0
0
Bit 28
EXR
1
1
1
0
0
0
0
0
0
0
0
1
1
1
Bit 27
MSB
0
0
0
1
1
1
1
0
0
0
0
1
1
1
Bit 26
Bit 25
Bit 24
Bit 23
Bit 4
LSB
1
1
0
1
0
1
0
1
0
1
0
1
0
0
Bit 3-0
SUB LSBs*
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Input Voltage
V
IN
> 9/8 V
REF
9/8 V
REF
V
REF
+ 1LSB
V
REF
3/4V
REF
+ 1LSB
3/4V
REF
1/2V
REF
+ 1LSB
1/2V
REF
1/4V
REF
+ 1LSB
1/4V
REF
0
+
/0
–1LSB
–1/8 V
REF
V
IN
< –1/8 V
REF
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
...
...
...
...
...
...
...
...
...
...
...
...
...
...
Figure 3. Output Data Timing
to the value corresponding to 1.125 V
REF
. For input
voltages below –0.125 V
REF
, the conversion result is
clamped to the value corresponding to –0.125 V
REF
.
Frequency Rejection Selection (F
O
Pin Connection)
The LTC2400 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz
±
2% or 60Hz
±
2%. For 60Hz rejec-
tion, F
O
(Pin 8) should be connected to GND (Pin 4) while
for 50Hz rejection the F
O
pin should be connected to V
CC
(Pin1).
MSB
EXT
SIG
“0”
1
2
3
4
5
27
28
32
BIT 0
BIT 27
BIT 4
LSB
24
BIT 28
BIT 29
BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2400 F03
Hi-Z
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