參數(shù)資料
型號(hào)： LTC2400
廠商： Linear Technology Corporation
英文描述： 24-Bit uPower No Latency ADC in SO-8
中文描述： 24位uPower在ADC的無延遲蘇- 8
文件頁數(shù)： 32/40頁
文件大?。?/td> 455K
代理商： LTC2400
32
LTC2400
TYPICAL APPLICATIO
N
S
*
DIN1
DIN2
DIN3
DIN4
*
**********************
* Start GETDATA Routine *
**********************
*
ORG
INIT1
LDS
LDAA
*
STAA
LDAA
STAA
*
*DDRD's bit 5 is a 1 so that port D's SS* pin is a general output
LDAA
#$50
STAA
SPCR
*
*
*
*
GETDATA PSHX
PSHY
PSHA
LDX
#$0
*
LDY
#$1000
BCLR
PORTD, Y %00100000
*
TRFLP1
LDAA
#$0
STAA
SPDR
*
WAIT1
LDAA
SPSR
EQU
EQU
EQU
EQU
$00
$01
$02
$03
This memory location holds the LTC2400's bits 31 - 24
This memory location holds the LTC2400's bits 23 - 16
This memory location holds the LTC2400's bits 15 - 08
This memory location holds the LTC2400's bits 07 - 00
$C000
#$CFFF
#$2F
Program start location
Top of C page RAM, beginning location of stack
–,–,1,0;1,1,1,1
–, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
Keeps SS* a logic high when DDRD, bit 5 is set
–,–,1,1;1,0,0,0
SS*, SCK, MOSI are configured as Outputs
MISO, TxD, RxD are configured as Inputs
PORTD
#$38
DDRD
The SPI is configured as Master, CPHA = 0, CPOL = 0
and the clock rate is E/2
(This assumes an E-Clock frequency of 4MHz. For higher E-
Clock frequencies, change the above value of $50 to a value
that ensures the SCK frequency is 2MHz or less.)
The X register is used as a pointer to the memory locations
that hold the conversion data
This sets the SS* output bit to a logic
low, selecting the LTC2400
Load accumulator A with a null byte for SPI transfer
This writes the byte in the SPI data register and starts
the transfer
This loop waits for the SPI to complete a serial
transfer/exchange by reading the SPI Status Register
The SPIF (SPI transfer complete flag) bit is the SPSR's MSB
and is set to one at the end of an SPI transfer. The branch
will occur while SPIF is a zero.
Load accumulator A with the current byte of LTC2400 data
that was just received
Transfer the LTC2400's data to memory
Increment the pointer
#DIN4+1 Has the last byte been transferred/exchanged
TRFLP1
If the last byte has not been reached, then proceed to the
next byte for transfer/exchange
PORTD,Y %00100000 This sets the SS* output bit to a logic high,
de-selecting the LTC2400
Restore the A register
Restore the Y register
Restore the X register
BPL
WAIT1
*
*
LDAA
SPDR
STAA
INX
CPX
BNE
0,X
*
BSET
*
PULA
PULY
PULX
RTS
Figure 34. This is an Example of 68HC11 Code That Captures the LTC2400’s
Conversion Results Over the SPI Serial Interface Shown in Figure 33
相關(guān)PDF資料
PDF描述
LTC2400C 24-Bit uPower No Latency ADC in SO-8
LTC2400CS8 24-Bit uPower No Latency ADC in SO-8
LTC2400I 24-Bit uPower No Latency ADC in SO-8
LTC3456 2-Cell, Multi-Output DC/DC Converter with USB Power Manager
LTC3456EUF ECONOLINE: RSZ/P - 1kVDC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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