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參數(shù)資料
| 型號： | LTC2400I |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 24-Bit uPower No Latency ADC in SO-8 |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SO-8 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 455K |
| 代理商： | LTC2400I |
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18
LTC2400
APPLICATIO
S I
N
FOR
ATIO
U
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
EOCtest
after the falling edge of CS
(if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t
EOCtest
is 23
μ
s
if the device is using its internal oscillator (F
0
= logic LOW
or HIGH). If F
O
is driven by an external oscillator of
frequency f
EOSC
, then t
EOCtest
is 3.6/f
EOSC
. If CS is pulled
HIGH before time t
EOCtest
, the device remains in the sleep
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
W
U
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
SDO
SCK
(INTERNAL)
CS
>t
EOCtest
MSB
EXR
SIG
BIT 8
TEST EOC
TEST EOC
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
EOC
BIT 0
SLEEP
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DATA OUTPUT
CONVERSION
CONVERSION
SLEEP
2400 F09
<t
EOCtest
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND
CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1
μ
F
2.7V TO 5.5V
LTC2400
V
CC
10k
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
TEST EOC
Figure 9. Internal Serial Clock, Reduced Data Output Length
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| LTC2400IS8#PBF | 功能描述:IC A/D CONV 24BIT MICRPWR 8-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| LTC2400IS8#PBF | 制造商:Linear Technology 功能描述:IC ADC 24BIT SOIC-8 制造商:Linear Technology 功能描述:IC, ADC, 24BIT, SOIC-8 |
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