參數(shù)資料
型號(hào)： LTC2400I
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： 24-Bit uPower No Latency ADC in SO-8
中文描述： 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8
封裝： 0.150 INCH, PLASTIC, SO-8
文件頁(yè)數(shù)： 19/40頁(yè)
文件大小： 455K
代理商： LTC2400I
19
LTC2400
APPLICATIO
S I
N
FOR
ATIO
U
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2400’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes HI-Z after outputting a LOW signal, the
LTC2400’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes HI-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as t
EOCtest
), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
W
U
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground (Pin 4),
simplifying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
CC
exceeds 2.2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
SDO
SCK
(INTERNAL)
CS
LSB
24
MSB
EXR
SIG
BIT 4
BIT 0
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
2400 F10
V
CC
F
O
V
REF
SCK
V
IN
SDO
GND
CS
V
REF
0.1V TO V
CC
V
IN
–0.12V
REF
TO 1.12V
REF
1
μ
F
2.7V TO 5.5V
LTC2400
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
Figure 10. Internal Serial Clock, Continuous Operation
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