參數(shù)資料
型號: LTC2400IS8
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 24-Bit uPower No Latency ADC in SO-8
中文描述: 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8
封裝: 0.150 INCH, PLASTIC, SO-8
文件頁數(shù): 13/40頁
文件大?。?/td> 455K
代理商: LTC2400IS8
13
LTC2400
Table 3. LTC2400 State Duration
State
CONVERT
Operating Mode
Internal Oscillator
Duration
133ms
F
O
= LOW
(60Hz Rejection)
F
O
= HIGH
(50Hz Rejection)
F
O
= External Oscillator
with Frequency f
EOSC
kHz
(f
EOSC
/2560 Rejection)
160ms
External Oscillator
20480/f
EOSC
s
SLEEP
DATA OUTPUT
As Long As CS = HIGH Until CS = 0 and SCK
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 256/f
EOSC
ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 32/f
SCK
ms
(32 SCK cycles)
Internal Serial Clock
F
O
= LOW/HIGH
(Internal Oscillator)
F
O
= External Oscillator with
Frequency f
EOSC
kHz
External Serial Clock with
Frequency f
SCK
kHz
APPLICATIO
S I
N
FOR
ATIO
U
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2400 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the F
O
pin and turns off the internal oscillator. The
frequency f
EOSC
of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2400 provides better than 110dB
normal mode rejection in a frequency range f
EOSC
/2560
±
4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/2560
is shown in Figure 4.
Whenever an external clock is not present at the F
O
pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2400
W
U
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
–12
–8
–4
0
4
8
12
R
2400 G25
–60
–70
–80
–90
–100
–110
–120
–130
–140
Figure 4. LTC2400 Normal Mode Rejection When
Using an External Oscillator of Frequency f
EOSC
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state as a
function of F
O
.
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