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參數(shù)資料
| 型號(hào)： | LTC2404C |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 18-Bit Universal Bus Driver With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 4-/8-Channel 24位ADC的無延遲uPower |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 351K |
| 代理商： | LTC2404C |
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14
LTC2404/LTC2408
Channel Selection
Typically, CSADC and CSMUX are tied together or CSADC
is inverted and drives CSMUX. SCK and CLK are tied
together and driven with a common clock signal. During
channel selection, CSMUX is HIGH. Data is shifted into the
D
IN
pin on the rising edge of CLK, see Figure 3. Table 3
shows the bit combinations for channel selection. In order
to enable the multiplexer output, CSMUX must be pulled
LOW. The multiplexer should be programmed after the
previous conversion is complete. In order to guarantee the
conversion is complete, the multiplexer addressing should
be delayed a minimum t
CONV
(approximately 133ms for a
60Hz notch) after the data out is read.
While the multiplexer is being programmed, the ADC is in
a low power sleep state. Once the MUX addressing is
complete, the data from the preceding conversion can be
read. A new conversion cycle is initiated following the data
read cycle with the analog input tied to the newly selected
channel.
APPLICATIO
S I
N
FOR
ATIO
U
W
U
Table 2. LTC2404/LTC2408 Output Data Format
Bit 31
Input Voltage
EOC
V
IN
> 9/8 V
REF
0
9/8 V
REF
0
V
REF
+ 1LSB
0
V
REF
0
3/4V
REF
+ 1LSB
0
3/4V
REF
0
1/2V
REF
+ 1LSB
0
1/2V
REF
0
1/4V
REF
+ 1LSB
0
1/4V
REF
0
0
+
/0
–
0
–1LSB
0
–1/8 V
REF
0
V
IN
< –1/8 V
REF
0
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.
Bit 30
DMY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 29
SIG
1
1
1
1
1
1
1
1
1
1
1/0**
0
0
0
Bit 28
EXR
1
1
1
0
0
0
0
0
0
0
0
1
1
1
Bit 27
MSB
0
0
0
1
1
1
1
0
0
0
0
1
1
1
Bit 26
Bit 25
Bit 24
Bit 23
…
Bit 4
LSB
1
1
0
1
0
1
0
1
0
1
0
1
0
0
Bit 3-0
SUB LSBs*
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
...
...
...
...
...
...
...
...
...
...
...
...
...
...
Table 3. Logic Table for Channel Selection
CHANNEL STATUS
All Off
CH0
CH1
CH2
CH3
CH4*
CH5*
CH6*
CH7*
*Not used for the LTC2404.
EN
0
1
1
1
1
1
1
1
1
D2
X
0
0
0
0
1
1
1
1
D1
X
0
0
1
1
0
0
1
1
D0
X
0
1
0
1
0
1
0
1
Frequency Rejection Selection (F
O
Pin Connection)
The LTC2404/LTC2408 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz
±
2% or 60Hz
±
2%. For
60Hz rejection, F
O
(Pin 26) should be connected to GND
(Pin 1) while for 50Hz rejection the F
O
pin should be
connected to V
CC
(Pin2).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2404I | 18-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85 |
| LTC2408 | 18-Bit Universal Bus Driver With 3-State Outputs 56-TVSOP -40 to 85 |
| LTC2408C | 20-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85 |
| LTC2408CG | 4-/8-Channel 24-Bit uPower No Latency ADCs |
| LTC2408I | 20-Bit Universal Bus Driver With 3-State Outputs 56-TVSOP -40 to 85 |
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