參數(shù)資料
型號: LTC2404C
廠商: Linear Technology Corporation
英文描述: 18-Bit Universal Bus Driver With 3-State Outputs 56-SSOP -40 to 85
中文描述: 4-/8-Channel 24位ADC的無延遲uPower
文件頁數(shù): 30/36頁
文件大?。?/td> 351K
代理商: LTC2404C
30
LTC2404/LTC2408
APPLICATIO
S I
FOR
ATIO
U
W
U
U
DIN1
DIN2
DIN3
DIN4
MUX
*
***************************************
* Start GETDATA Routine
***************************************
*
ORG
$C000
*
LDS
$CFFF
INIT1
LDAA
#$2F
*
STAA
PORTD
LDAA
#$38
STAA
DDRD
*
* DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
LDAA
#$50
STAA
SPCR
*
*
*
*
GETDATA PSHX
PSHY
PSHA
LDX
#$0
*
LDY
#$1000
*
*******************************
* The next routine sends data to the *
* LTC2408 an sets its MUX channel *
*******************************
*
LDAA
$MUX
ORAA
#$08
STAA
SPDR
*
WAITMUX LDAA
SPSR
BPL
*
***************************************
* Enable the LTC2408
***************************************
*
BCLR
PORTD,Y %00100000 This sets the SS* output bit to a logic
*
*
***************************************
* The next short loop waits for the
* LTC2408’s conversion to finish before
* starting the SPI data transfer
***************************************
*
CONVEND LDAA
PORTD
ANDA
#%00000100
*
*
*
BNE
CONVEND
*
EQU
EQU
EQU
EQU
EQU
$00
$01
$02
$03
$04
This memory location holds the LTC2408’s bits 31 - 24
This memory location holds the LTC2408’s bits 23 - 16
This memory location holds the LTC2408’s bits 15 - 08
This memory location holds the LTC2408’s bits 07 - 00
This memory location holds the MUX address data
*
Program start location
Top of C page RAM, beginning location of stack
-,-,1,0;1,1,1,1
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
Keeps SS* a logic high when DDRD, bit 5 is set
-,-,1,1;1,0,0,0
SS* , SCK, MOSI are configured as Outputs
MISO, TxD, RxD are configured as Inputs
The SPI is configured as Master, CPHA = 0, CPOL = 0
and the clock rate is E/2
(This assumes an E-Clock frequency of 4MHz. For higher
E-Clock frequencies, change the above value of $50 to a
value that ensures the SCK frequency is 2MHz or less.)
The X register is used as a pointer to the memory
locations that hold the conversion data
Retrieve MUX address
Set the MUX’s ENABLE bit
Transfer Accum. A contents to SPI register to initiate
serial transfer
Get SPI transfer status
WAITMUX If the transfer is not finished, read status
*
low, selecting the LTC2408
*
*
*
Retrieve the contents of port D
Look at bit 2
Bit 2 = Hi; the LTC2408’s conversion is not
complete
Bit 2 = Lo; the LTC2408’s conversion is complete
Branch to the loop’s beginning while bit 2 remains
high
相關(guān)PDF資料
PDF描述
LTC2404I 18-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85
LTC2408 18-Bit Universal Bus Driver With 3-State Outputs 56-TVSOP -40 to 85
LTC2408C 20-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85
LTC2408CG 4-/8-Channel 24-Bit uPower No Latency ADCs
LTC2408I 20-Bit Universal Bus Driver With 3-State Outputs 56-TVSOP -40 to 85
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