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參數(shù)資料
| 型號(hào)： | LTC2408C |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 20-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85 |
| 中文描述： | 4-/8-Channel 24位ADC的無(wú)延遲uPower |
| 文件頁(yè)數(shù)： | 13/36頁(yè) |
| 文件大?。?/td> | 351K |
| 代理商： | LTC2408C |
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13
LTC2404/LTC2408
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CSADC is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device,
CSADC must first be driven LOW. EOC is seen at the SDO
pin of the device once CSADC is pulled LOW. EOC changes
in real time from HIGH to LOW at the completion of a
conversion. This signal may be used as an interrupt for an
external microcontroller. Bit 31 (EOC) can be captured on
the first rising edge of SCK. Bit 30 is shifted out of the
device on the first falling edge of SCK. The final data bit
(Bit 0) is shifted out on the falling edge of the 31st SCK and
may be latched on the rising edge of the 32nd SCK pulse.
On the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating a new conversion cycle has been initiated. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the V
IN
pin is maintained within
the –0.3V to (V
CC
+ 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from –0.125 V
REF
to 1.125 V
REF
.
For input voltages
greater than 1.125 V
REF
, the conversion result is clamped
to the value corresponding to 1.125 V
REF
. For input
voltages below –0.125 V
REF
, the conversion result is
clamped to the value corresponding to –0.125 V
REF
.
APPLICATIO
S I
N
FOR
ATIO
U
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CSADC pin is
LOW. This bit is HIGH during the conversion and goes
LOW when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0
≤
V
IN
≤
V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
W
U
Figure 3. Typical Data Input/Output Timing
EOC
“0”
SDO
SCK/CLK
D
IN
CSMUX/CSADC
MSB
LSB
D2
EN
D1
D0
EXT
SIG
BIT 30
BIT 31
BIT 0
24048 F03
HI-Z
DON’T CARE
t
CONV
HI-Z
Table 1. LTC2404/LTC2408 Status Bits
Bit 31
EOC
0
0
0
0
Bit 30
DMY
0
0
0
0
Bit 29
SIG
1
1
1/0
0
Bit 28
EXR
1
0
0
1
Input Range
V
IN
> V
REF
0 < V
IN
≤
V
REF
V
IN
= 0
+
/0
–
V
IN
< 0
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
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