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參數資料
| 型號： | LTC2408C |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 20-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85 |
| 中文描述： | 4-/8-Channel 24位ADC的無延遲uPower |
| 文件頁數： | 18/36頁 |
| 文件大?。?/td> | 351K |
| 代理商： | LTC2408C |
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18
LTC2404/LTC2408
APPLICATIO
S I
N
FOR
ATIO
U
W
U
While the device is in the sleep state, prior to entering the
data output state, the user may program the multiplexer.
As shown in Figure 7, the multiplexer channel is selected
by serial shifting a 4-bit word into the D
IN
pin on the rising
edge of CLK (CLK is tied to SCK). The first bit is an enable
bit that must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the falling edge of CSMUX, the new channel is
selected and will be valid for the first conversion performed
following the data output state. Clock signals applied to the
CLK pin while CSMUX is LOW (during the data output
state) will have no effect on the channel selection. Further-
more, if D
IN
is held LOW or CLK is held LOW during the
sleep state, the channel selection is unchanged.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. The device remains in the sleep state until the first
rising edge of SCK is seen while CSADC is LOW. Data is
shifted out the SDO pin on each falling edge of SCK. This
enables external circuitry to latch the output on the rising
edge of SCK. EOC can be latched on the first rising edge
of SCK and the last bit of the conversion result can be
latched on the 32nd rising edge of SCK. On the 32nd falling
edge of SCK, the device begins a new conversion. SDO
goes HIGH (EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CSADC may remain
LOW and EOC monitored as an end-of-conversion inter-
rupt. Alternatively, CSADC may be driven HIGH setting
SDO to HI-Z. As described above, CSADC may be pulled
LOW at any time in order to monitor the conversion status.
For each of these operations, CSMUX may be tied to
CSADC without affecting the selected channel.
At the conclusion of the data output cycle, the converter
enters a user transparent calibration cycle prior to actually
performing a conversion on the selected input channel.
This enables a 66ms (for 60Hz notch frequency) look ahead
time for the multiplexer input. Following the data output
cycle, the multiplexer input channel may be selected any
time in this 66ms window by pulling CSADC HIGH and
serial shifting data into the D
IN
pin, see Figure 8.
While the device is performing the internal calibration, it is
sensitive to ground current disturbances. Error currents
flowing in the ground pin may lead to offset errors. If the
SCK pin is toggling during the calibration, these ground
disturbances will occur. The solution is to either drive the
multiplexer clock input (CLK) separately from the ADC
clock input (SCK), or program the multiplexer in the first
1ms following the data output cycle. The remaining 65ms
may be used to allow the input signal to settle.
Figure 7. External Serial Clock Timing Diagram
SCK/CLK
SDO
D
IN
CSADC/
CSMUX
V
CC
F
O
V
REF
CSMUX
CSADC
SCK
CLK
MUXOUT
ADCIN
D
IN
SDO
GND
0.1V
TO V
CC
–0.12V
REF
TO 1.12V
REF
CH0
TO CH7
2.7V TO 5.5V
LTC2404/LTC2408
MSB
SUB
LSB
EXR
SIG
BIT0
LSB
BIT4
BIT27 BIT26
BIT28
BIT29
BIT30
BIT31
24048 F07
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
TEST EOC
DON’T CARE
DON’T CARE
EN
D2
D1
D0
HI-Z
HI-Z
TEST EOC
HI-Z
TEST EOC
CS
SCK
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