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參數(shù)資料
| 型號： | LTC2410IGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 24-Bit No Latency ADC with Differential Input and Differential Reference |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 6/44頁 |
| 文件大?。?/td> | 778K |
| 代理商： | LTC2410IGN |
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LTC2410
6
GND (Pins 1, 7, 8, 9, 10, 15, 16):
Ground. Multiple
ground pins internally connected for optimum ground
current flow and V
CC
decoupling. Connect each one of
these pins to a ground plane through a low impedance
connection.
V
CC
(Pin 2):
Positive Supply Voltage. Bypass to GND
(Pin1) with a 10
μ
F tantalum capacitor in parallel with
0.1
μ
F ceramic capacitor as close to the part as possible.
REF
+
(Pin 3), REF
–
(Pin 4):
Differential Reference Input.
The voltage on these pins can have any value between GND
and V
CC
as long as the reference positive input, REF
+
, is
maintained more positive than the reference negative
input, REF
–
, by at least 0.1V.
IN
+
(Pin 5), IN
–
(Pin 6):
Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and V
CC
+ 0.3V. Within these limits the
converter bipolar input range (V
IN
= IN
+
– IN
–
) extends
from –0.5 (V
REF
) to 0.5 (V
REF
). Outside this input range
the converter produces unique overrange and underrange
output codes.
CS (Pin 11):
Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12):
Three-State Digital Output. During the Data
Output period this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
CC
) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13):
Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
F
O
(Pin 14):
Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency f
EOSC
/2560.
PIU
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