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參數(shù)資料
| 型號： | LTC2412 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit Universal Bus Driver With 3-State Outputs 48-SSOP -40 to 85 |
| 中文描述： | 2路差分輸入24位ADC的無延遲局副局長 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 409K |
| 代理商： | LTC2412 |
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LTC2412
15
2412f
Frequency Rejection Selection (F
O
)
The LTC2412 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz
±
2% or 60Hz
±
2%. For 60Hz rejec-
tion, F
O
should be connected to GND while for 50Hz
rejection the F
O
pin should be connected to V
CC
.
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2412 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the F
O
pin and turns off the internal oscillator. The
frequency f
EOSC
of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2412 provides better than 110dB
normal mode rejection in a frequency range f
EOSC
/2560
±
4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/2560
is shown in Figure 4.
Whenever an external clock is not present at the F
O
pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2412
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
Figure 4. LTC2412 Normal Mode Rejection When
Using an External Oscillator of Frequency f
EOSC
APPLICATIU
W
U
U
Table 2. LTC2412 Output Data Format
Differential Input Voltage
V
IN
*
V
IN
*
≥
0.5 V
REF
**
0.5 V
REF
** – 1LSB
0.25 V
REF
**
0.25 V
REF
** – 1LSB
0
–1LSB
Bit 31
EOC
0
0
Bit 30
CH0/CH1
0/1
0/1
Bit 29
SIG
1
1
Bit 28
MSB
1
0
Bit 27
Bit 26
Bit 25
…
Bit 0
0
1
0
1
0
1
…
…
0
1
0
0
0/1
0/1
1
1
0
0
1
0
0
1
0
1
…
…
0
1
0
0
0/1
0/1
1
0
0
1
0
1
0
1
0
1
…
…
0
1
–0.25 V
REF
**
–0.25 V
REF
** – 1LSB
–0.5 V
REF
**
V
IN
* < –0.5 V
REF
**
*The differential input voltage V
IN
= IN
+
– IN
–
.
**The differential reference voltage V
REF
= REF
+
– REF
–
.
0
0
0/1
0/1
0
0
1
1
1
0
0
1
0
1
…
…
0
1
0
0
0/1
0/1
0
0
1
0
0
1
0
1
0
1
…
…
0
1
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
EOSC
/2560(%)
–12
–8
–4
0
4
8
12
N
2412 F04
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
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