參數(shù)資料
型號(hào): LTC2412CGN
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): ADC
英文描述: 16-Bit Universal Bus Driver With 3-State Outputs 48-TVSOP -40 to 85
中文描述: 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁(yè)數(shù): 16/36頁(yè)
文件大?。?/td> 409K
代理商: LTC2412CGN
LTC2412
16
2412f
APPLICATIU
W
U
U
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of F
O
.
SERIAL INTERFACE PINS
The LTC2412 transmits the conversion results and re-
ceives the start of conversion command through a syn-
chronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 13) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2412 creates its own serial clock by
dividing the internal conversion clock by 8. In the External
SCK mode of operation, the SCK pin is used as input. The
internal or external SCK mode is selected on power-up and
then reselected every time a HIGH-to-LOW transition is
detected at the CS pin. If SCK is HIGH or floating at power-
up or during this transition, the converter enters the inter-
nal SCK mode. If SCK is LOW at power-up or during this
transition, the converter enters the external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 11) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 11), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2412 will abort any serial data
transfer in progress and start a new conversion cycle
Table 3. LTC2412 State Duration
State
CONVERT
Operating Mode
Internal Oscillator
Duration
133ms, Output Data Rate
7.5 Readings/s
F
O
= LOW
(60Hz Rejection)
F
O
= HIGH
(50Hz Rejection)
F
O
= External Oscillator
with Frequency f
EOSC
kHz
(f
EOSC
/2560 Rejection)
160ms, Output Data Rate
6.2 Readings/s
External Oscillator
20510/f
EOSC
s, Output Data Rate
f
EOSC
/20510 Readings/s
SLEEP
DATA OUTPUT
As Long As CS = HIGH
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 256/f
EOSC
ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 32/f
SCK
ms
(32 SCK cycles)
Internal Serial Clock
F
O
= LOW/HIGH
(Internal Oscillator)
F
O
= External Oscillator with
Frequency f
EOSC
kHz
External Serial Clock with
Frequency f
SCK
kHz
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