參數(shù)資料
型號(hào)： LTC2412CGN
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 16-Bit Universal Bus Driver With 3-State Outputs 48-TVSOP -40 to 85
中文描述： 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝： 0.150 INCH, PLASTIC, SSOP-16
文件頁(yè)數(shù)： 25/36頁(yè)
文件大?。?/td> 409K
代理商： LTC2412CGN
LTC2412
25
2412f
APPLICATIU
W
U
U
of input multiplexers, wires, connectors or sensors, the
LTC2412 can maintain its exceptional accuracy while
operating with relative large values of source resistance as
shown in Figures 13 and 14. These measured results may
be slightly different from the first order approximation
suggested earlier because they include the effect of the
actual second order input network together with the non-
linear settling process of the input amplifiers. For small C
IN
values, the settling on IN
+
and IN
–
occurs almost indepen-
dently and there is little benefit in trying to match the
source impedance for the two pins.
Larger values of input capacitors (C
IN
> 0.01
μ
F) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When F
O
= LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 1.8M
which will
generate a gain error of approximately 0.28ppm at full-
scale for each ohm of source resistance driving IN
+
or IN.
When F
O
= HIGH (internal oscillator and 50Hz notch), the
typical differential input resistance is 2.16M
which will
generate a gain error of approximately 0.23ppm at full-
scale for each ohm of source resistance driving IN
+
or IN.
When F
O
is driven by an external oscillator with a fre-
quency f
EOSC
(external conversion clock operation), the
typical differential input resistance is 0.28 10
12
/f
EOSC
and each ohm of source resistance driving IN
+
or IN
–
will
result in 1.78 10
–6
f
EOSC
ppm gain error at full-scale. The
effect of the source resistance on the two input pins is
additive with respect to this gain error. The typical +FS and
–FS errors as a function of the sum of the source resis-
tance seen by IN
+
and IN
–
for large values of C
IN
are shown
in Figures 15 and 16.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN
+
and IN
–
and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the con-
verter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C
IN
capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN
+
and IN
–
pins. When F
O
= LOW
(internal oscillator and 60Hz notch), every 1
mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.28ppm. When F
O
= HIGH (internal oscillator and 50Hz
notch), every 1
mismatch in source impedance trans-
forms a full-scale common mode input signal into a differ-
ential mode input signal of 0.23ppm. When F
O
is driven by
an external oscillator with a frequency f
EOSC
, every 1
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 1.78 10
–6
f
EOSC
ppm. Figure 17 shows the
typical offset error due to input common mode voltage for
Figure 15. +FS Error vs R
SOURCE
at IN
+
or IN
–
(Large C
IN
)
Figure 16. –FS Error vs R
SOURCE
at IN
+
or IN
–
(Large C
IN
)
R
SOURCE
(
)
0 100 200 300 400 500 600 700 800 9001000
+
R
)
2412 F15
300
240
180
120
60
0
V
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 3.75V
IN
–
= 1.25V
F
O
= GND
T
A
= 25
°
C
C
IN
= 0.01
μ
F
C
IN
= 0.1
μ
F
C
IN
= 1
μ
F, 10
μ
F
R
SOURCE
(
)
0 100 200 300 400 500 600 700 800 9001000
–
R
)
2412 F16
0
–60
–120
–180
–240
–300
V
CC
= 5V
REF
= 5V
REF
–
= GND
IN
+
= 1.25V
IN
–
= 3.75V
F
O
= GND
T
A
= 25
°
C
C
IN
= 0.01
μ
F
C
IN
= 0.1
μ
F
C
IN
= 1
μ
F, 10
μ
F
相關(guān)PDF資料
PDF描述
LTC2414 2-Channel Differential Input 24-Bit No Latency DS ADC
LTC2418 Replaced by SN74ALVCH16374 : 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-SSOP -40 to 85
LTC2412IGN 2-Channel Differential Input 24-Bit No Latency DS ADC
LTC2420CS8 20-Bit uPower No Latency ADC in SO-8
LTC2420IS8 20-Bit uPower No Latency ADC in SO-8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2412CGN#PBF 功能描述:IC ADC 2CH DIFF-IN 24BIT 16SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁(yè)面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6
LTC2412CGN#PBF 制造商:Linear Technology 功能描述:IC, ADC, 24BIT, SSOP-16
LTC2412CGN#TR 功能描述:IC CONV A/D 24B 2CH DIFF 16-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極
LTC2412CGN#TRPBF 功能描述:IC ADC 2CH DIFF-IN 24BIT 16SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極
LTC2412CGNPBF 制造商:Linear Technology 功能描述:ADC,LTC2412 24bit diff D-S 2 ch SPI SSOP
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*