the IN+
參數(shù)資料
型號(hào)： LTC2412IGN#TRPBF
廠(chǎng)商： Linear Technology
文件頁(yè)數(shù)： 19/36頁(yè)
文件大小： 0K
描述： IC ADC 2CH DIFF-IN 24BIT 16SSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
配用： DC746A-ND - BOARD DELTA SIGMA ADC LTC2412
LTC2412
26
2412f
APPLICATIO S I FOR ATIO
WU
U
various values of source resistance imbalance between
the IN+ and IN– pins when large CIN values are used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
±10nA max), results
in a small offset shift. A 100
source resistance will create
a 0.1
V typical and 1V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2412 samples the differential
reference pins REF+ and REF– transfering small amount of
charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 0.01F), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01F) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When FO = LOW
(internal oscillator and 60Hz notch), the typical differential
reference resistance is 1.3M
which will generate a gain
error of approximately 0.38ppm at full-scale for each ohm
of source resistance driving REF+ or REF–. When FO =
HIGH (internal oscillator and 50Hz notch), the typical
differential reference resistance is 1.56M
which will
generate a gain error of approximately 0.32ppm at full-
scale for each ohm of source resistance driving REF+ or
REF–. When FO is driven by an external oscillator with a
frequency fEOSC (external conversion clock operation), the
typical differential reference resistance is 0.20 1012/
fEOSC and each ohm of source resistance drving REF+ or
REF– will result in 2.47 10–6 fEOSCppm gain error at full-
scale. The effect of the source resistance on the two
reference pins is additive with respect to this gain error.
The typical +FS and –FS errors for various combinations
of source resistance seen by the REF+ and REF– pins and
external capacitance CREF connected to these pins are
shown in Figures 18, 19, 20 and 21.
Figure 17. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance
Imbalance (
RIN = RSOURCEIN+ – RSOURCEIN–) for
Large CIN Values (CIN ≥ 1F)
VINCM (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
OFFSET
ERROR
(ppm
OF
V
REF
)
2412 F17
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
FO = GND
TA = 25°C
RSOURCEIN– = 500
CIN = 10F
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = IN– = VINCM
A:
RIN = +400
B:
RIN = +200
C:
RIN = +100
D:
RIN = 0
E:
RIN = –100
F:
RIN = –200
G:
RIN = –400
A
B
C
D
E
F
G
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