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參數(shù)資料
| 型號： | LTC2412IGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 2CH DIFF-IN 24BIT 16SSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | DC746A-ND - BOARD DELTA SIGMA ADC LTC2412 |
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LTC2412
30
2412f
APPLICATIO S I FOR ATIO
WU
U
Input Bandwidth
The combined effect of the internal Sinc4 digital filter and
of the analog and digital autocalibration circuits deter-
mines the LTC2412 input bandwidth. When the internal
oscillator is used with the notch set at 60Hz (FO = LOW),
the 3dB input bandwidth is 3.63Hz. When the internal
oscillator is used with the notch set at 50Hz (FO = HIGH),
the 3dB input bandwidth is 3.02Hz. If an external conver-
sion clock generator of frequency fEOSC is connected to the
FO pin, the 3dB input bandwidth is 0.236 10–6 fEOSC.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled very
accurately by a first order filter with the pole located at the
3dB frequency. When the internal oscillator is used, the
shape of the LTC2412 input bandwidth is shown in Fig-
ure 31 for FO = LOW and FO = HIGH. When an external
oscillator of frequency fEOSC is used, the shape of the
LTC2412 input bandwidth can be derived from Figure 31,
FO = LOW curve in which the horizontal axis is scaled by
fEOSC/153600.
The conversion noise (800nVRMS typical for VREF = 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is
62.75nV/
√Hz for an infinite bandwidth source and
86.1nV/
√Hz for a single 0.5MHz pole source. From these
numbers, it is clear that particular attention must be given
to the design of external amplification circuits. Such
circuits face the simultaneous requirements of very low
bandwidth (just a few Hz) in order to reduce the output
referred noise and relatively high bandwidth (at least
500kHz) necessary to drive the input switched-capacitor
network. A possible solution is a high gain, low bandwidth
amplifier stage followed by a high bandwidth unity-gain
buffer.
When external amplifiers are driving the LTC2412, the
ADC input referred system noise calculation can be simpli-
fied by Figure 32. The noise of an amplifier driving the
LTC2412 input pin can be modeled as a band limited white
noise source. Its bandwidth can be approximated by the
bandwidth of a single pole lowpass filter with a corner
frequency fi. The amplifier noise spectral density is ni.
From Figure 32, using fi as the x-axis selector, we can find
on the y-axis the noise equivalent bandwidth freqi of the
Figure 29. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 30. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 31. Input Signal Bandwidth
Using the Internal Oscillator
OUTPUT DATA RATE (READINGS/SEC)
0
102030405060708090 100
RESOLUTION
(BITS)
2412 F29
24
23
22
21
20
19
18
17
16
15
14
13
12
VREF = 5V
VCC = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
TA = 25°C
RESOLUTION = LOG2(VREF/NOISERMS)
VREF = 2.5V
OUTPUT DATA RATE (READINGS/SEC)
0
102030405060708090 100
RESOLUTION
(BITS)
2412 F30
22
20
18
16
14
12
10
8
TA = 25°C
VCC = 5V
REF – = GND
VINCM = 0.5 REF
+
–0.5V VREF < VIN < 0.5 VREF
FO = EXTERNAL OSCILLATOR
VREF = 2.5V
VREF = 5V
RESOLUTION =
LOG2(VREF/INLMAX)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
INPUT
SIGNAL
ATTENUATION
(dB)
2412 F31
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
FO = HIGH
FO = LOW
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