參數(shù)資料
型號(hào)： LTC2413IGN#TRPBF
廠商： Linear Technology
文件頁數(shù)： 16/44頁
文件大小： 0K
描述： IC A/D CONV 24BIT MICRPWR 16SSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，雙極
LTC2413
23
sn2413 2413fs
APPLICATIO S I FOR ATIO
WU
U
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.
PRESERVING THE CONVERTER ACCURACY
The LTC2413 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
extreme accuracy capability of this part, some simple
precautions are desirable.
Digital Signal Levels
The LTC2413’s digital interface is easy to use. Its digital
inputs (FO, CS and SCK in External SCK mode of operation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100
s.However,someconsiderationsarerequiredtotake
advantage of the exceptional accuracy and low supply
current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
in External SCK mode of operation) is within this range, the
LTC2413 power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation, it is recommended to drive all digital input
signals to full CMOS levels [VIL < 0.4V and VIH >
(VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the LTC2413
pins may severely disturb the analog to digital conversion
process. Undershoot and overshoot can occur because of
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2413.
For reference, on a regular FR-4 board, signal propagation
Figure 13. CS Capacitance vs tSAMPLE
Figure 14. CS Capacitance vs Output Rate
Figure 15. CS Capacitance vs Supply Current
CAPACITANCE ON CS (pF)
1
5
6
7
1000
10000
2413 F13
4
3
10
100
100000
2
1
0
t SAMPLE
(SEC)
VCC = 5V
VCC = 3V
CAPACITANCE ON CS (pF)
0
SAMPLE
RATE
(Hz)
3
4
5
1000
100000
2413 F14
2
1
0
10
100
10000
6
7
8
VCC = 5V
VCC = 3V
CAPACITANCE ON CS (pF)
1
0
SUPPLY
CURRENT
(
A
RMS
)
50
100
150
200
250
300
10
100
1000
10000
2413 F15
100000
VCC = 5V
VCC = 3V
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