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參數(shù)資料
| 型號： | LTC2413IGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 24-Bit No Latency ADC, with Simultaneous 50Hz/60Hz Rejection |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 14/44頁 |
| 文件大小： | 454K |
| 代理商： | LTC2413IGN |
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LTC2413
14
sn2413 2413fs
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
–
pins is maintained
within the –0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 V
REF
to
+FS = 0.5 V
REF
. For differential input voltages greater than
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Simultaneous Frequency Rejection
The LTC2413 internal oscillator provides better than 87dB
normal mode rejection over the range of 49Hz to 61.2Hz as
shown in Figure 4. For this simultaneous 50Hz/60Hz
rejection, F
O
should be connected to GND.
When a fundamental rejection frequency different from
the range 49Hz to 61.2Hz is required or when the converter
must be sychronized with an outside source, the LTC2413
can operate with an external conversion clock. The conveter
automatically detects the presence of an external clock
signal at the F
O
pin and turns off the internal oscillator. The
frequency f
EOSC
of the external signal must be at least
2560Hz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods, t
HEO
and t
LEO
,
are observed.
Table 2. LTC2413 Output Data Format
Differential Input Voltage
V
IN
*
V
IN
*
≥
0.5 V
REF
**
0.5 V
REF
** – 1LSB
0.25 V
REF
**
0.25 V
REF
** – 1LSB
0
–1LSB
Bit 31
EOC
0
0
Bit 30
DMY
0
0
Bit 29
SIG
1
1
Bit 28
MSB
1
0
Bit 27
Bit 26
Bit 25
…
Bit 0
0
1
0
1
0
1
…
…
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
…
…
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
…
…
0
1
–0.25 V
REF
**
–0.25 V
REF
** – 1LSB
–0.5 V
REF
**
V
IN
* < –0.5 V
REF
**
*The differential input voltage V
IN
= IN
+
– IN
–
.
**The differential reference voltage V
REF
= REF
+
– REF
–
.
0
0
0
0
0
0
1
1
1
0
0
1
0
1
…
…
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
1
…
…
0
1
Figure 3. Output Data Timing
APPLICATIU
W
U
U
MSB
SIG
“0”
1
2
3
4
5
26
27
32
BIT 0
BIT 27
BIT 5
LSB
24
BIT 28
BIT 29
BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2413 F03
Hi-Z
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