參數(shù)資料
型號： LTC2415-1IGN
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 24-Bit No Latency ADCs with Differential Input and Differential Reference
中文描述： 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝： 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù)： 27/40頁
文件大小： 605K
代理商： LTC2415-1IGN
LTC2415/LTC2415-1
27
sn2415 24151fs
APPLICATIU
W
U
U
Figure 18. LTC2415/LTC2415-1 Equivalent Analog Input Circuit
Figure 19. An RC Network at IN
+
and IN
–
Figure 21. –FS Error vs R
SOURCE
at IN
+
or IN
(Small C
)
Figure 20. +FS Error vs R
SOURCE
at IN
+
or IN
(Small C
IN
)
I IN
V
V
0 5
.
V
R
I IN
V
V
0 5
.
V
R
0 5
.
I REF
V
V
V
R
V
V
V
R
2
I REF
V
V
R
V
V
R
where
V
REF
AVG
IN
INCM
REFCM
EQ
AVG
)
IN
INCM
REFCM
EQ
AVG
)
REF
INCM
0 5
.
REFCM
EQ
IN
REF
EQ
AVG
REF
INCM
EQ
REFCM
IN
REF
EQ
+
+
)
)
=
+
=
+
=
+
=
+
+
1 5
.
1 5
.
2
:
=
.
.
.
/
.
REF
REF
+
V
REF
REF
V
IN
IN
+
V
IN
IN
R
R
M
M
INTERNAL OSCILLATOR
INTERNAL OSCILLATOR
)
INTERNAL OSCILLATOR
Hz Notch F
Hz Notch F
50
LOW
HIGH
R
f
EXTERNAL OSCILLATOR
R
REFCM
IN
INCM
EQ
O
EQ
O
EQ
EOSC
EQ
=
+
2
=
=
2
=
=
=
=
(
(
)
)
=
(
3 97
=
+
+
3 61
4 32
60
0 555 10
12
LTC2415
LTC2415
M
Hz
Hz Notch F
60
LOW
O
50
/
=
(
)
LTC2415-1
C
IN
2415 F19
V
INCM
+ 0.5V
IN
R
SOURCE
IN
+
LTC2415/
LTC2415-1
C
PAR
C
IN
V
INCM
– 0.5V
IN
R
SOURCE
IN
–
C
PAR
20pF
R
SOURCE
(
)
1
10
100
1k
10k
100k
+
R
)
2415 F20
50
40
30
20
10
0
V
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 5V
IN
–
= 2.5V
F
O
= GND
T
A
= 25
°
C
C
IN
= 0.01
μ
F
C
IN
= 0.001
μ
F
C
IN
= 100pF
C
IN
= 0pF
R
SOURCE
(
)
1
10
100
1k
10k
100k
–
R
)
2415 F21
0
–10
–20
–30
–40
–50
V
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= GND
IN
–
= 2.5V
F
O
= GND
T
A
= 25
°
C
C
IN
= 0.01
μ
F
C
IN
= 0.001
μ
F
C
IN
= 100pF
C
IN
= 0pF
V
REF
+
V
IN
+
V
CC
R
SW
(TYP)
20k
I
LEAK
I
LEAK
V
CC
V
CC
I
LEAK
I
LEAK
R
SW
(TYP)
20k
C
18pF
(TYP)
R
SW
(TYP)
20k
I
LEAK
I
IN
+
V
IN
–
I
IN
–
I
REF
+
I
REF
–
2415 F18
I
LEAK
V
CC
I
LEAK
I
LEAK
SWITCHING FREQUENCY
f
= 76800Hz INTERNAL
OSCILLATOR (LTC2415)
(F
O
= LOW OR HIGH)
f
= 69900Hz INTERNAL
OSCILLATOR (LTC2415-1)
(F
O
= LOW)
f
SW
= 0.5 f
EOSC
EXTERNAL OSCILLATOR
V
REF
–
R
SW
(TYP)
20k
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 18 shows the
mathematical expressions for the average bias currents
flowing through the IN
+
and IN
–
pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 19. The C
PAR
capacitor
includes the LTC2415/LTC2415-1 pin capacitance (5pF
typical) plus the capacitance of the test fixture used to
obtain the results shown in Figures 20 and 21. A careful
implementation can bring the total input capacitance (C
IN
+ C
PAR
) closer to 5pF thus achieving better performance
than the one predicted by Figures 20 and 21. For simplic-
ity, two distinct situations can be considered.
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