參數(shù)資料
型號： LTC2415-1IGN
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 24-Bit No Latency ADCs with Differential Input and Differential Reference
中文描述： 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝： 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù)： 31/40頁
文件大小： 605K
代理商： LTC2415-1IGN
LTC2415/LTC2415-1
31
sn2415 24151fs
APPLICATIU
tance is 1.43M
. When F
O
is driven by an external
oscillator with a frequency f
EOSC
(external conversion
clock operation), the typical differential reference resis-
tance is 0.20 10
12
/f
EOSC
and each ohm of source
resistance driving REF
+
or REF
–
will result in
2.47 10
–6
f
EOSC
ppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by the
REF
+
and REF
–
pins and external capacitance C
REF
connected to these pins are shown in Figures 25, 26, 27
and28.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F
O
= LOW (internal oscillator and 60Hz notch), every
100
of source resistance driving REF
+
or REF
–
translates
into about 1.34ppm additional INL error. For the LTC2415,
when F
O
= HIGH (internal oscillator and 50Hz notch), every
100
of source resistance driving REF
+
or REF
–
translates
into about 1.1ppm additional INL error; and for the
LTC2415-1 operating with simultaneous 50Hz/60Hz re-
jection, every 100
of source resistance leads to an
additional 1.22ppm of additional INL error. When F
O
is
driven by an external oscillator with a frequency f
EOSC
,
every 100
of source resistance driving REF
+
or REF
–
translates into about 8.73 10
–6
f
EOSC
ppm additional INL
error. Figure26 shows the typical INL error due to the
source resistance driving the REF
+
or REF
–
pins when
W
U
U
Figure 29. INL vs Differential Input Voltage (V
IN
= IN
+
– IN
–
) and Reference
Source Resistance (R
SOURCE
at REF
+
and REF
–
for Large C
REF
Values (C
REF
≥
1
μ
F)
V
INDIF
/V
REFDIF
–0.5–0.4–0.3–0.2–0.1 0
0.1 0.2 0.3 0.4 0.5
I
R
)
15
12
9
6
3
0
–3
–6
–9
–12
–15
V
= 5V
REF+ = 5V
REF– = GND
V
INCM
= 0.5 (IN
+
+ IN
–
) = 2.5V
F
O
C
REF
= 10
μ
F
T
A
= 25
°
C
R
SOURCE
= 1000
R
SOURCE
= 500
R
SOURCE
= 100
2415 F29
large C
REF
values are used. The effect of the source
resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
impedance for the REF
+
and REF
–
pins does not help the
gain or the INL error. The user is thus advised to minimize
the combined source impedance driving the REF
+
and
REF
–
pins rather than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/
°
C) are used for the external source impedance
seen by REF
+
and REF
–
, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(
±
10nA max), results in a small gain error. A 100
source
resistance will create a 0.05
μ
V typical and 0.5
μ
V maxi-
mum full-scale error.
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